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#ifndef _PP2_GOP_DEF_H_
#define _PP2_GOP_DEF_H_

/***********/
/*GMAC REGS */
/***********/

/* Port Mac Control0 */
#define PP2_GMAC_PORT_CTRL0_REG			(0x0000)
#define PP2_GMAC_PORT_CTRL0_PORTEN_OFFS		0
#define PP2_GMAC_PORT_CTRL0_PORTEN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL0_PORTEN_OFFS)

#define PP2_GMAC_PORT_CTRL0_PORTTYPE_OFFS		1
#define PP2_GMAC_PORT_CTRL0_PORTTYPE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL0_PORTTYPE_OFFS)

#define PP2_GMAC_PORT_CTRL0_FRAMESIZELIMIT_OFFS		2
#define PP2_GMAC_PORT_CTRL0_FRAMESIZELIMIT_MASK    \
		(0x00001fff << PP2_GMAC_PORT_CTRL0_FRAMESIZELIMIT_OFFS)

#define PP2_GMAC_PORT_CTRL0_COUNT_EN_OFFS		15
#define PP2_GMAC_PORT_CTRL0_COUNT_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL0_COUNT_EN_OFFS)

/* Port Mac Control1 */
#define PP2_GMAC_PORT_CTRL1_REG			(0x0004)
#define PP2_GMAC_PORT_CTRL1_EN_RX_CRC_CHECK_OFFS	0
#define PP2_GMAC_PORT_CTRL1_EN_RX_CRC_CHECK_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL1_EN_RX_CRC_CHECK_OFFS)

#define PP2_GMAC_PORT_CTRL1_EN_PERIODIC_FC_XON_OFFS		1
#define PP2_GMAC_PORT_CTRL1_EN_PERIODIC_FC_XON_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL1_EN_PERIODIC_FC_XON_OFFS)

#define PP2_GMAC_PORT_CTRL1_MGMII_MODE_OFFS		2
#define PP2_GMAC_PORT_CTRL1_MGMII_MODE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL1_MGMII_MODE_OFFS)

#define PP2_GMAC_PORT_CTRL1_PFC_CASCADE_PORT_ENABLE_OFFS		3
#define PP2_GMAC_PORT_CTRL1_PFC_CASCADE_PORT_ENABLE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL1_PFC_CASCADE_PORT_ENABLE_OFFS)

#define PP2_GMAC_PORT_CTRL1_DIS_EXCESSIVE_COL_OFFS		4
#define PP2_GMAC_PORT_CTRL1_DIS_EXCESSIVE_COL_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL1_DIS_EXCESSIVE_COL_OFFS)

#define PP2_GMAC_PORT_CTRL1_GMII_LOOPBACK_OFFS		5
#define PP2_GMAC_PORT_CTRL1_GMII_LOOPBACK_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL1_GMII_LOOPBACK_OFFS)

#define PP2_GMAC_PORT_CTRL1_PCS_LOOPBACK_OFFS		6
#define PP2_GMAC_PORT_CTRL1_PCS_LOOPBACK_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL1_PCS_LOOPBACK_OFFS)

#define PP2_GMAC_PORT_CTRL1_FC_SA_ADDR_LO_OFFS		7
#define PP2_GMAC_PORT_CTRL1_FC_SA_ADDR_LO_MASK    \
		(0x000000ff << PP2_GMAC_PORT_CTRL1_FC_SA_ADDR_LO_OFFS)

#define PP2_GMAC_PORT_CTRL1_EN_SHORT_PREAMBLE_OFFS		15
#define PP2_GMAC_PORT_CTRL1_EN_SHORT_PREAMBLE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL1_EN_SHORT_PREAMBLE_OFFS)

/* Port Mac Control2 */
#define PP2_GMAC_PORT_CTRL2_REG			(0x0008)
#define PP2_GMAC_PORT_CTRL2_SGMII_MODE_OFFS		0
#define PP2_GMAC_PORT_CTRL2_SGMII_MODE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL2_SGMII_MODE_OFFS)

#define PP2_GMAC_PORT_CTRL2_FC_MODE_OFFS		1
#define PP2_GMAC_PORT_CTRL2_FC_MODE_MASK    \
		(0x00000003 << PP2_GMAC_PORT_CTRL2_FC_MODE_OFFS)

#define PP2_GMAC_PORT_CTRL2_PCS_EN_OFFS		3
#define PP2_GMAC_PORT_CTRL2_PCS_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL2_PCS_EN_OFFS)

#define PP2_GMAC_PORT_CTRL2_RGMII_MODE_OFFS		4
#define PP2_GMAC_PORT_CTRL2_RGMII_MODE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL2_RGMII_MODE_OFFS)

#define PP2_GMAC_PORT_CTRL2_DIS_PADING_OFFS		5
#define PP2_GMAC_PORT_CTRL2_DIS_PADING_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL2_DIS_PADING_OFFS)

#define PP2_GMAC_PORT_CTRL2_PORTMACRESET_OFFS		6
#define PP2_GMAC_PORT_CTRL2_PORTMACRESET_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL2_PORTMACRESET_OFFS)

#define PP2_GMAC_PORT_CTRL2_TX_DRAIN_OFFS		7
#define PP2_GMAC_PORT_CTRL2_TX_DRAIN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL2_TX_DRAIN_OFFS)

#define PP2_GMAC_PORT_CTRL2_EN_MII_ODD_PRE_OFFS		8
#define PP2_GMAC_PORT_CTRL2_EN_MII_ODD_PRE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL2_EN_MII_ODD_PRE_OFFS)

#define PP2_GMAC_PORT_CTRL2_CLK_125_BYPS_EN_OFFS		9
#define PP2_GMAC_PORT_CTRL2_CLK_125_BYPS_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL2_CLK_125_BYPS_EN_OFFS)

#define PP2_GMAC_PORT_CTRL2_PRBS_CHECK_EN_OFFS		10
#define PP2_GMAC_PORT_CTRL2_PRBS_CHECK_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL2_PRBS_CHECK_EN_OFFS)

#define PP2_GMAC_PORT_CTRL2_PRBS_GEN_EN_OFFS		11
#define PP2_GMAC_PORT_CTRL2_PRBS_GEN_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL2_PRBS_GEN_EN_OFFS)

#define PP2_GMAC_PORT_CTRL2_SELECT_DATA_TO_TX_OFFS		12
#define PP2_GMAC_PORT_CTRL2_SELECT_DATA_TO_TX_MASK    \
		(0x00000003 << PP2_GMAC_PORT_CTRL2_SELECT_DATA_TO_TX_OFFS)

#define PP2_GMAC_PORT_CTRL2_EN_COL_ON_BP_OFFS		14
#define PP2_GMAC_PORT_CTRL2_EN_COL_ON_BP_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL2_EN_COL_ON_BP_OFFS)

#define PP2_GMAC_PORT_CTRL2_EARLY_REJECT_MODE_OFFS		15
#define PP2_GMAC_PORT_CTRL2_EARLY_REJECT_MODE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL2_EARLY_REJECT_MODE_OFFS)

/* Port Auto-negotiation Configuration */
#define PP2_GMAC_PORT_AUTO_NEG_CFG_REG			(0x000c)
#define PP2_GMAC_PORT_AUTO_NEG_CFG_FORCE_LINK_DOWN_OFFS		0
#define PP2_GMAC_PORT_AUTO_NEG_CFG_FORCE_LINK_DOWN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_FORCE_LINK_DOWN_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_FORCE_LINK_UP_OFFS		1
#define PP2_GMAC_PORT_AUTO_NEG_CFG_FORCE_LINK_UP_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_FORCE_LINK_UP_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_EN_PCS_AN_OFFS		2
#define PP2_GMAC_PORT_AUTO_NEG_CFG_EN_PCS_AN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_EN_PCS_AN_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_AN_BYPASS_EN_OFFS		3
#define PP2_GMAC_PORT_AUTO_NEG_CFG_AN_BYPASS_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_AN_BYPASS_EN_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_INBAND_RESTARTAN_OFFS		4
#define PP2_GMAC_PORT_AUTO_NEG_CFG_INBAND_RESTARTAN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_INBAND_RESTARTAN_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_SET_MII_SPEED_OFFS		5
#define PP2_GMAC_PORT_AUTO_NEG_CFG_SET_MII_SPEED_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_SET_MII_SPEED_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_SET_GMII_SPEED_OFFS		6
#define PP2_GMAC_PORT_AUTO_NEG_CFG_SET_GMII_SPEED_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_SET_GMII_SPEED_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_EN_AN_SPEED_OFFS		7
#define PP2_GMAC_PORT_AUTO_NEG_CFG_EN_AN_SPEED_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_EN_AN_SPEED_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_ADV_PAUSE_OFFS		9
#define PP2_GMAC_PORT_AUTO_NEG_CFG_ADV_PAUSE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_ADV_PAUSE_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_ADV_ASM_PAUSE_OFFS		10
#define PP2_GMAC_PORT_AUTO_NEG_CFG_ADV_ASM_PAUSE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_ADV_ASM_PAUSE_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_EN_FC_AN_OFFS			11
#define PP2_GMAC_PORT_AUTO_NEG_CFG_EN_FC_AN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_EN_FC_AN_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_SET_FULL_DX_OFFS		12
#define PP2_GMAC_PORT_AUTO_NEG_CFG_SET_FULL_DX_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_SET_FULL_DX_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_EN_FDX_AN_OFFS		13
#define PP2_GMAC_PORT_AUTO_NEG_CFG_EN_FDX_AN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_EN_FDX_AN_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_PHY_MODE_OFFS		14
#define PP2_GMAC_PORT_AUTO_NEG_CFG_PHY_MODE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_AUTO_NEG_CFG_PHY_MODE_OFFS)

#define PP2_GMAC_PORT_AUTO_NEG_CFG_CHOOSE_SAMPLE_TX_CONFIG_OFFS		15
#define PP2_GMAC_PORT_AUTO_NEG_CFG_CHOOSE_SAMPLE_TX_CONFIG_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_AUTO_NEG_CFG_CHOOSE_SAMPLE_TX_CONFIG_OFFS)

/* Port Status0 */
#define PP2_GMAC_PORT_STATUS0_REG				(0x0010)
#define PP2_GMAC_PORT_STATUS0_LINKUP_OFFS		0
#define PP2_GMAC_PORT_STATUS0_LINKUP_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_LINKUP_OFFS)

#define PP2_GMAC_PORT_STATUS0_GMIISPEED_OFFS		1
#define PP2_GMAC_PORT_STATUS0_GMIISPEED_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_GMIISPEED_OFFS)

#define PP2_GMAC_PORT_STATUS0_MIISPEED_OFFS		2
#define PP2_GMAC_PORT_STATUS0_MIISPEED_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_MIISPEED_OFFS)

#define PP2_GMAC_PORT_STATUS0_FULLDX_OFFS		3
#define PP2_GMAC_PORT_STATUS0_FULLDX_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_FULLDX_OFFS)

#define PP2_GMAC_PORT_STATUS0_RXFCEN_OFFS		4
#define PP2_GMAC_PORT_STATUS0_RXFCEN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_RXFCEN_OFFS)

#define PP2_GMAC_PORT_STATUS0_TXFCEN_OFFS		5
#define PP2_GMAC_PORT_STATUS0_TXFCEN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_TXFCEN_OFFS)

#define PP2_GMAC_PORT_STATUS0_PORTRXPAUSE_OFFS		6
#define PP2_GMAC_PORT_STATUS0_PORTRXPAUSE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_PORTRXPAUSE_OFFS)

#define PP2_GMAC_PORT_STATUS0_PORTTXPAUSE_OFFS		7
#define PP2_GMAC_PORT_STATUS0_PORTTXPAUSE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_PORTTXPAUSE_OFFS)

#define PP2_GMAC_PORT_STATUS0_PORTIS_DOINGPRESSURE_OFFS		8
#define PP2_GMAC_PORT_STATUS0_PORTIS_DOINGPRESSURE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_PORTIS_DOINGPRESSURE_OFFS)

#define PP2_GMAC_PORT_STATUS0_PORTBUFFULL_OFFS		9
#define PP2_GMAC_PORT_STATUS0_PORTBUFFULL_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_PORTBUFFULL_OFFS)

#define PP2_GMAC_PORT_STATUS0_SYNCFAIL10MS_OFFS		10
#define PP2_GMAC_PORT_STATUS0_SYNCFAIL10MS_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_SYNCFAIL10MS_OFFS)

#define PP2_GMAC_PORT_STATUS0_ANDONE_OFFS		11
#define PP2_GMAC_PORT_STATUS0_ANDONE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_ANDONE_OFFS)

#define PP2_GMAC_PORT_STATUS0_INBAND_AUTONEG_BYPASSACT_OFFS		12
#define PP2_GMAC_PORT_STATUS0_INBAND_AUTONEG_BYPASSACT_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_STATUS0_INBAND_AUTONEG_BYPASSACT_OFFS)

#define PP2_GMAC_PORT_STATUS0_SERDESPLL_LOCKED_OFFS		13
#define PP2_GMAC_PORT_STATUS0_SERDESPLL_LOCKED_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_SERDESPLL_LOCKED_OFFS)

#define PP2_GMAC_PORT_STATUS0_SYNCOK_OFFS		14
#define PP2_GMAC_PORT_STATUS0_SYNCOK_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_SYNCOK_OFFS)

#define PP2_GMAC_PORT_STATUS0_SQUELCHNOT_DETECTED_OFFS		15
#define PP2_GMAC_PORT_STATUS0_SQUELCHNOT_DETECTED_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS0_SQUELCHNOT_DETECTED_OFFS)

/* Port Serial Parameters Configuration */
#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_REG			(0x0014)
#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_UNIDIRECTIONAL_ENABLE_OFFS	0
#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_UNIDIRECTIONAL_ENABLE_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERIAL_PARAM_CFG_UNIDIRECTIONAL_ENABLE_OFFS)

#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_RETRANSMIT_COLLISION_DOMAIN_OFFS	1
#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_RETRANSMIT_COLLISION_DOMAIN_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERIAL_PARAM_CFG_RETRANSMIT_COLLISION_DOMAIN_OFFS)

#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_PUMA2_BTS1444_EN_OFFS		2
#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_PUMA2_BTS1444_EN_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERIAL_PARAM_CFG_PUMA2_BTS1444_EN_OFFS)

#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_FORWARD_802_3X_FC_EN_OFFS		3
#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_FORWARD_802_3X_FC_EN_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERIAL_PARAM_CFG_FORWARD_802_3X_FC_EN_OFFS)

#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_BP_EN_OFFS		4
#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_BP_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_SERIAL_PARAM_CFG_BP_EN_OFFS)

#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_RX_NEGEDGE_SAMPLE_EN_OFFS		5
#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_RX_NEGEDGE_SAMPLE_EN_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERIAL_PARAM_CFG_RX_NEGEDGE_SAMPLE_EN_OFFS)

#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_COL_DOMAIN_LIMIT_OFFS		6
#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_COL_DOMAIN_LIMIT_MASK    \
		(0x0000003f << \
		PP2_GMAC_PORT_SERIAL_PARAM_CFG_COL_DOMAIN_LIMIT_OFFS)

#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_PERIODIC_TYPE_SELECT_OFFS		12
#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_PERIODIC_TYPE_SELECT_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERIAL_PARAM_CFG_PERIODIC_TYPE_SELECT_OFFS)

#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_PER_PRIORITY_FC_EN_OFFS		13
#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_PER_PRIORITY_FC_EN_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERIAL_PARAM_CFG_PER_PRIORITY_FC_EN_OFFS)

#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_TX_STANDARD_PRBS7_OFFS		14
#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_TX_STANDARD_PRBS7_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERIAL_PARAM_CFG_TX_STANDARD_PRBS7_OFFS)

#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_REVERSE_PRBS_RX_OFFS		15
#define PP2_GMAC_PORT_SERIAL_PARAM_CFG_REVERSE_PRBS_RX_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERIAL_PARAM_CFG_REVERSE_PRBS_RX_OFFS)

/* Port Fifo Configuration 0 */
#define PP2_GMAC_PORT_FIFO_CFG_0_REG				(0x0018)
#define PP2_GMAC_PORT_FIFO_CFG_0_TX_FIFO_HIGH_WM_OFFS		0
#define PP2_GMAC_PORT_FIFO_CFG_0_TX_FIFO_HIGH_WM_MASK    \
		(0x000000ff << \
		PP2_GMAC_PORT_FIFO_CFG_0_TX_FIFO_HIGH_WM_OFFS)

#define PP2_GMAC_PORT_FIFO_CFG_0_TX_FIFO_LOW_WM_OFFS		8
#define PP2_GMAC_PORT_FIFO_CFG_0_TX_FIFO_LOW_WM_MASK    \
		(0x000000ff << \
		PP2_GMAC_PORT_FIFO_CFG_0_TX_FIFO_LOW_WM_OFFS)

/* Port Fifo Configuration 1 */
#define PP2_GMAC_PORT_FIFO_CFG_1_REG				(0x001c)
#define PP2_GMAC_PORT_FIFO_CFG_1_RX_FIFO_MAX_TH_OFFS		0
#define PP2_GMAC_PORT_FIFO_CFG_1_RX_FIFO_MAX_TH_MASK    \
		(0x0000003f << PP2_GMAC_PORT_FIFO_CFG_1_RX_FIFO_MAX_TH_OFFS)

#define PP2_GMAC_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_OFFS		6
#define PP2_GMAC_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_MASK    \
		(0x000000ff << PP2_GMAC_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_OFFS)

#define PP2_GMAC_PORT_FIFO_CFG_1_PORT_EN_FIX_EN_OFFS		15
#define PP2_GMAC_PORT_FIFO_CFG_1_PORT_EN_FIX_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_FIFO_CFG_1_PORT_EN_FIX_EN_OFFS)

/* Port Serdes Configuration0 */
#define PP2_GMAC_PORT_SERDES_CFG0_REG				(0x0028)
#define PP2_GMAC_PORT_SERDES_CFG0_SERDESRESET_OFFS		0
#define PP2_GMAC_PORT_SERDES_CFG0_SERDESRESET_MASK    \
		(0x00000001 << PP2_GMAC_PORT_SERDES_CFG0_SERDESRESET_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_PU_TX_OFFS		1
#define PP2_GMAC_PORT_SERDES_CFG0_PU_TX_MASK    \
		(0x00000001 << PP2_GMAC_PORT_SERDES_CFG0_PU_TX_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_PU_RX_OFFS		2
#define PP2_GMAC_PORT_SERDES_CFG0_PU_RX_MASK    \
		(0x00000001 << PP2_GMAC_PORT_SERDES_CFG0_PU_RX_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_PU_PLL_OFFS		3
#define PP2_GMAC_PORT_SERDES_CFG0_PU_PLL_MASK    \
		(0x00000001 << PP2_GMAC_PORT_SERDES_CFG0_PU_PLL_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_PU_IVREF_OFFS		4
#define PP2_GMAC_PORT_SERDES_CFG0_PU_IVREF_MASK    \
		(0x00000001 << PP2_GMAC_PORT_SERDES_CFG0_PU_IVREF_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_TESTEN_OFFS		5
#define PP2_GMAC_PORT_SERDES_CFG0_TESTEN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_SERDES_CFG0_TESTEN_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_DPHER_EN_OFFS		6
#define PP2_GMAC_PORT_SERDES_CFG0_DPHER_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_SERDES_CFG0_DPHER_EN_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_RUDI_INVALID_ENABLE_OFFS		7
#define PP2_GMAC_PORT_SERDES_CFG0_RUDI_INVALID_ENABLE_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERDES_CFG0_RUDI_INVALID_ENABLE_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_ACK_OVERRIDE_ENABLE_OFFS		8
#define PP2_GMAC_PORT_SERDES_CFG0_ACK_OVERRIDE_ENABLE_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERDES_CFG0_ACK_OVERRIDE_ENABLE_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_CONFIG_WORD_ENABLE_OFFS		9
#define PP2_GMAC_PORT_SERDES_CFG0_CONFIG_WORD_ENABLE_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERDES_CFG0_CONFIG_WORD_ENABLE_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_SYNC_FAIL_INT_ENABLE_OFFS		10
#define PP2_GMAC_PORT_SERDES_CFG0_SYNC_FAIL_INT_ENABLE_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERDES_CFG0_SYNC_FAIL_INT_ENABLE_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_MASTER_MODE_ENABLE_OFFS		11
#define PP2_GMAC_PORT_SERDES_CFG0_MASTER_MODE_ENABLE_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERDES_CFG0_MASTER_MODE_ENABLE_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_TERM75_TX_OFFS		12
#define PP2_GMAC_PORT_SERDES_CFG0_TERM75_TX_MASK    \
		(0x00000001 << PP2_GMAC_PORT_SERDES_CFG0_TERM75_TX_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_OUTAMP_OFFS		13
#define PP2_GMAC_PORT_SERDES_CFG0_OUTAMP_MASK    \
		(0x00000001 << PP2_GMAC_PORT_SERDES_CFG0_OUTAMP_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_BTS712_FIX_EN_OFFS		14
#define PP2_GMAC_PORT_SERDES_CFG0_BTS712_FIX_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_SERDES_CFG0_BTS712_FIX_EN_OFFS)

#define PP2_GMAC_PORT_SERDES_CFG0_BTS156_FIX_EN_OFFS		15
#define PP2_GMAC_PORT_SERDES_CFG0_BTS156_FIX_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_SERDES_CFG0_BTS156_FIX_EN_OFFS)

/* Port Serdes Configuration1 */
#define PP2_GMAC_PORT_SERDES_CFG1_REG			(0x002c)
#define PP2_GMAC_PORT_SERDES_CFG1_SMII_RX_10MB_CLK_EDGE_SEL_OFFS	0
#define PP2_GMAC_PORT_SERDES_CFG1_SMII_RX_10MB_CLK_EDGE_SEL_MASK    \
		(0x00000001 << \
		PP2_GMAC_GMAC_PORT_SERDES_CFG1_SMII_RX_10MB_CLK_EDGE_SEL_OFFS)

#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_SMII_TX_10MB_CLK_EDGE_SEL_OFFS	1
#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_SMII_TX_10MB_CLK_EDGE_SEL_MASK    \
		(0x00000001 << \
		PP2_GMAC_GMAC_PORT_SERDES_CFG1_SMII_TX_10MB_CLK_EDGE_SEL_OFFS)

#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_MEN_OFFS		2
#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_MEN_MASK    \
		(0x00000003 << PP2_GMAC_GMAC_PORT_SERDES_CFG1_MEN_OFFS)

#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_VCMS_OFFS		4
#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_VCMS_MASK    \
		(0x00000001 << PP2_GMAC_GMAC_PORT_SERDES_CFG1_VCMS_OFFS)

#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_USE_SIGDET_OFFS		5
#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_USE_SIGDET_MASK    \
		(0x00000001 << \
		PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_USE_SIGDET_OFFS)

#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_EN_CRS_MASK_TX_OFFS		6
#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_EN_CRS_MASK_TX_MASK    \
		(0x00000001 << \
		PP2_GMAC_GMAC_PORT_SERDES_CFG1_EN_CRS_MASK_TX_OFFS)

#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_ENABLE_OFFS		7
#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_ENABLE_MASK    \
		(0x00000001 << PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_ENABLE_OFFS)

#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_PHY_ADDRESS_OFFS	8
#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_PHY_ADDRESS_MASK    \
		(0x0000001f << \
		PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_PHY_ADDRESS_OFFS)

#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_SIGDET_POLARITY_OFFS	13
#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_SIGDET_POLARITY_MASK    \
		(0x00000001 << \
		PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_SIGDET_POLARITY_OFFS)

#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_INTERRUPT_POLARITY_OFFS	14
#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_INTERRUPT_POLARITY_MASK    \
		(0x00000001 << \
	PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_INTERRUPT_POLARITY_OFFS)

#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_SERDES_POLARITY_OFFS	15
#define PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_SERDES_POLARITY_MASK    \
		(0x00000001 << \
		PP2_GMAC_GMAC_PORT_SERDES_CFG1_100FX_PCS_SERDES_POLARITY_OFFS)

/* Port Serdes Configuration2 */
#define PP2_GMAC_PORT_SERDES_CFG2_REG				(0x0030)
#define PP2_GMAC_PORT_SERDES_CFG2_AN_ADV_CONFIGURATION_OFFS	0
#define PP2_GMAC_PORT_SERDES_CFG2_AN_ADV_CONFIGURATION_MASK    \
		(0x0000ffff << \
		PP2_GMAC_PORT_SERDES_CFG2_AN_ADV_CONFIGURATION_OFFS)

/* Port Serdes Configuration3 */
#define PP2_GMAC_PORT_SERDES_CFG3_REG				(0x0034)
#define PP2_GMAC_PORT_SERDES_CFG3_ABILITY_MATCH_STATUS_OFFS		0
#define PP2_GMAC_PORT_SERDES_CFG3_ABILITY_MATCH_STATUS_MASK    \
		(0x0000ffff << \
		PP2_GMAC_PORT_SERDES_CFG3_ABILITY_MATCH_STATUS_OFFS)

/* Port Prbs Status */
#define PP2_GMAC_PORT_PRBS_STATUS_REG				(0x0038)
#define PP2_GMAC_PORT_PRBS_STATUS_PRBSCHECK_LOCKED_OFFS		0
#define PP2_GMAC_PORT_PRBS_STATUS_PRBSCHECK_LOCKED_MASK    \
		(0x00000001 << PP2_GMAC_PORT_PRBS_STATUS_PRBSCHECK_LOCKED_OFFS)

#define PP2_GMAC_PORT_PRBS_STATUS_PRBSCHECKRDY_OFFS		1
#define PP2_GMAC_PORT_PRBS_STATUS_PRBSCHECKRDY_MASK    \
		(0x00000001 << PP2_GMAC_PORT_PRBS_STATUS_PRBSCHECKRDY_OFFS)

/* Port Prbs Error Counter */
#define PP2_GMAC_PORT_PRBS_ERR_CNTR_REG				(0x003c)
#define PP2_GMAC_PORT_PRBS_ERR_CNTR_PRBSBITERRCNT_OFFS		0
#define PP2_GMAC_PORT_PRBS_ERR_CNTR_PRBSBITERRCNT_MASK    \
		(0x0000ffff << PP2_GMAC_PORT_PRBS_ERR_CNTR_PRBSBITERRCNT_OFFS)

/* Port Status1 */
#define PP2_GMAC_PORT_STATUS1_REG				(0x0040)
#define PP2_GMAC_PORT_STATUS1_MEDIAACTIVE_OFFS		0
#define PP2_GMAC_PORT_STATUS1_MEDIAACTIVE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_STATUS1_MEDIAACTIVE_OFFS)

/* Port Mib Counters Control */
#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_REG			(0x0044)
#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_MIB_COPY_TRIGGER_OFFS	0
#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_MIB_COPY_TRIGGER_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_MIB_CNTRS_CTRL_MIB_COPY_TRIGGER_OFFS)

#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_MIB_CLEAR_ON_READ__OFFS		1
#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_MIB_CLEAR_ON_READ__MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_MIB_CNTRS_CTRL_MIB_CLEAR_ON_READ__OFFS)

#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_RX_HISTOGRAM_EN_OFFS		2
#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_RX_HISTOGRAM_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_MIB_CNTRS_CTRL_RX_HISTOGRAM_EN_OFFS)

#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_TX_HISTOGRAM_EN_OFFS		3
#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_TX_HISTOGRAM_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_MIB_CNTRS_CTRL_TX_HISTOGRAM_EN_OFFS)

#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE__OFFS	4
#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE__MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE__OFFS)

#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_XCAT_BTS_340_EN__OFFS		5
#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_XCAT_BTS_340_EN__MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_MIB_CNTRS_CTRL_XCAT_BTS_340_EN__OFFS)

#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST_OFFS		6
#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST_OFFS)

#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522_OFFS		7
#define PP2_GMAC_PORT_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522_OFFS)

/* Port Mac Control3 */
#define PP2_GMAC_PORT_CTRL3_REG				(0x0048)
#define PP2_GMAC_PORT_CTRL3_BUF_SIZE_OFFS		0
#define PP2_GMAC_PORT_CTRL3_BUF_SIZE_MASK    \
		(0x0000003f << PP2_GMAC_PORT_CTRL3_BUF_SIZE_OFFS)

#define PP2_GMAC_PORT_CTRL3_IPG_DATA_OFFS		6
#define PP2_GMAC_PORT_CTRL3_IPG_DATA_MASK    \
		(0x000001ff << PP2_GMAC_PORT_CTRL3_IPG_DATA_OFFS)

#define PP2_GMAC_PORT_CTRL3_LLFC_GLOBAL_FC_ENABLE_OFFS		15
#define PP2_GMAC_PORT_CTRL3_LLFC_GLOBAL_FC_ENABLE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL3_LLFC_GLOBAL_FC_ENABLE_OFFS)

/* QSGMII */
#define PP2_GMAC_QSGMII_REG				(0x004c)
#define PP2_GMAC_QSGMII_QSGMII_REG_OFFS		0
#define PP2_GMAC_QSGMII_QSGMII_REG_MASK    \
		(0x0000ffff << PP2_GMAC_QSGMII_QSGMII_REG_OFFS)

/* Qsgmii Status */
#define PP2_GMAC_QSGMII_STATUS_REG				(0x0050)
#define PP2_GMAC_QSGMII_STATUS_QSGMII_STATUS_OFFS		0
#define PP2_GMAC_QSGMII_STATUS_QSGMII_STATUS_MASK    \
		(0x000000ff << PP2_GMAC_QSGMII_STATUS_QSGMII_STATUS_OFFS)

/* Qsgmii Prbs Counter */
#define PP2_GMAC_QSGMII_PRBS_CNTR_REG			(0x0054)
#define PP2_GMAC_QSGMII_PRBS_CNTR_QSGMII_PRBS_ERR_CNT_REG_OFFS		0
#define PP2_GMAC_QSGMII_PRBS_CNTR_QSGMII_PRBS_ERR_CNT_REG_MASK    \
		(0x0000ffff << \
		PP2_GMAC_QSGMII_PRBS_CNTR_QSGMII_PRBS_ERR_CNT_REG_OFFS)

/* Ccfc Port Speed Timer%p */
#define PP2_GMAC_CCFC_PORT_SPEED_TIMER_REG(t)		(0x0058 + t * 4)
#define PP2_GMAC_CCFC_PORT_SPEED_TIMER_PORTSPEEDTIMER_OFFS		0
#define PP2_GMAC_CCFC_PORT_SPEED_TIMER_PORTSPEEDTIMER_MASK    \
		(0x0000ffff << \
		PP2_GMAC_CCFC_PORT_SPEED_TIMER_PORTSPEEDTIMER_OFFS)

/* Fc Dsa Tag %n */
#define PP2_GMAC_FC_DSA_TAG_REG(n)			(0x0078 + 4 * n)
#define PP2_GMAC_FC_DSA_TAG_DSATAGREGN_OFFS		0
#define PP2_GMAC_FC_DSA_TAG_DSATAGREGN_MASK    \
		(0x0000ffff << PP2_GMAC_FC_DSA_TAG_DSATAGREGN_OFFS)

/* Link Level Flow Control Window Reg 0 */
#define PP2_GMAC_LINK_LEVEL_FLOW_CTRL_WINDOW_REG_0		(0x0088)
#define PP2_GMAC_LINK_LEVEL_FLOW_CTRL_WINDOW_REG_0_LLFC_FC_WINDOW_REG0_OFFS 0
#define PP2_GMAC_LINK_LEVEL_FLOW_CTRL_WINDOW_REG_0_LLFC_FC_WINDOW_REG0_MASK    \
		(0x0000ffff << \
	PP2_GMAC_LINK_LEVEL_FLOW_CTRL_WINDOW_REG_0_LLFC_FC_WINDOW_REG0_OFFS)

/* Link Level Flow Control Window Reg 1 */
#define PP2_GMAC_LINK_LEVEL_FLOW_CTRL_WINDOW_REG_1		(0x008c)
#define PP2_GMAC_LINK_LEVEL_FLOW_CTRL_WINDOW_REG_1_LLFC_FC_WINDOW_REG1_OFFS 0
#define PP2_GMAC_LINK_LEVEL_FLOW_CTRL_WINDOW_REG_1_LLFC_FC_WINDOW_REG1_MASK    \
		(0x00007fff << \
	PP2_GMAC_LINK_LEVEL_FLOW_CTRL_WINDOW_REG_1_LLFC_FC_WINDOW_REG1_OFFS)

#define PP2_GMAC_LINK_LEVEL_FLOW_CTRL_WINDOW_REG_1_LLFC_RATE_LIMIT_EN_OFFS 15
#define PP2_GMAC_LINK_LEVEL_FLOW_CTRL_WINDOW_REG_1_LLFC_RATE_LIMIT_EN_MASK    \
		(0x00000001 << \
	PP2_GMAC_LINK_LEVEL_FLOW_CTRL_WINDOW_REG_1_LLFC_RATE_LIMIT_EN_OFFS)

/* Port Mac Control4 */
#define PP2_GMAC_PORT_CTRL4_REG				(0x0090)
#define PP2_GMAC_PORT_CTRL4_EXT_PIN_GMII_SEL_OFFS		0
#define PP2_GMAC_PORT_CTRL4_EXT_PIN_GMII_SEL_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL4_EXT_PIN_GMII_SEL_OFFS)

#define PP2_GMAC_PORT_CTRL4_PREAMBLE_FIX_OFFS		1
#define PP2_GMAC_PORT_CTRL4_PREAMBLE_FIX_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL4_PREAMBLE_FIX_OFFS)

#define PP2_GMAC_PORT_CTRL4_SQ_DETECT_FIX_EN_OFFS		2
#define PP2_GMAC_PORT_CTRL4_SQ_DETECT_FIX_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL4_SQ_DETECT_FIX_EN_OFFS)

#define PP2_GMAC_PORT_CTRL4_FC_EN_RX_OFFS		3
#define PP2_GMAC_PORT_CTRL4_FC_EN_RX_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL4_FC_EN_RX_OFFS)

#define PP2_GMAC_PORT_CTRL4_FC_EN_TX_OFFS		4
#define PP2_GMAC_PORT_CTRL4_FC_EN_TX_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL4_FC_EN_TX_OFFS)

#define PP2_GMAC_PORT_CTRL4_DP_CLK_SEL_OFFS		5
#define PP2_GMAC_PORT_CTRL4_DP_CLK_SEL_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL4_DP_CLK_SEL_OFFS)

#define PP2_GMAC_PORT_CTRL4_SYNC_BYPASS_OFFS		6
#define PP2_GMAC_PORT_CTRL4_SYNC_BYPASS_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL4_SYNC_BYPASS_OFFS)

#define PP2_GMAC_PORT_CTRL4_QSGMII_BYPASS_ACTIVE_OFFS		7
#define PP2_GMAC_PORT_CTRL4_QSGMII_BYPASS_ACTIVE_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL4_QSGMII_BYPASS_ACTIVE_OFFS)

#define PP2_GMAC_PORT_CTRL4_COUNT_EXTERNAL_FC_EN_OFFS		8
#define PP2_GMAC_PORT_CTRL4_COUNT_EXTERNAL_FC_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL4_COUNT_EXTERNAL_FC_EN_OFFS)

#define PP2_GMAC_PORT_CTRL4_MARVELL_HEADER_EN_OFFS		9
#define PP2_GMAC_PORT_CTRL4_MARVELL_HEADER_EN_MASK    \
		(0x00000001 << PP2_GMAC_PORT_CTRL4_MARVELL_HEADER_EN_OFFS)

#define PP2_GMAC_PORT_CTRL4_LEDS_NUMBER_OFFS		10
#define PP2_GMAC_PORT_CTRL4_LEDS_NUMBER_MASK    \
		(0x0000003f << PP2_GMAC_PORT_CTRL4_LEDS_NUMBER_OFFS)

/* Port Serial Parameters 1 Configuration */
#define PP2_GMAC_PORT_SERIAL_PARAM_1_CFG_REG			(0x0094)
#define PP2_GMAC_PORT_SERIAL_PARAM_1_CFG_RX_STANDARD_PRBS7_OFFS		0
#define PP2_GMAC_PORT_SERIAL_PARAM_1_CFG_RX_STANDARD_PRBS7_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERIAL_PARAM_1_CFG_RX_STANDARD_PRBS7_OFFS)

#define PP2_GMAC_PORT_SERIAL_PARAM_1_CFG_FORWARD_PFC_EN_OFFS		1
#define PP2_GMAC_PORT_SERIAL_PARAM_1_CFG_FORWARD_PFC_EN_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERIAL_PARAM_1_CFG_FORWARD_PFC_EN_OFFS)

#define PP2_GMAC_PORT_SERIAL_PARAM_1_CFG_FORWARD_UNKNOWN_FC_EN_OFFS	2
#define PP2_GMAC_PORT_SERIAL_PARAM_1_CFG_FORWARD_UNKNOWN_FC_EN_MASK    \
		(0x00000001 << \
		PP2_GMAC_PORT_SERIAL_PARAM_1_CFG_FORWARD_UNKNOWN_FC_EN_OFFS)

/* Lpi Control 0 */
#define PP2_GMAC_LPI_CTRL_0_REG				(0x00c0)
#define PP2_GMAC_LPI_CTRL_0_LI_LIMIT_OFFS		0
#define PP2_GMAC_LPI_CTRL_0_LI_LIMIT_MASK    \
		(0x000000ff << PP2_GMAC_LPI_CTRL_0_LI_LIMIT_OFFS)

#define PP2_GMAC_LPI_CTRL_0_TS_LIMIT_OFFS		8
#define PP2_GMAC_LPI_CTRL_0_TS_LIMIT_MASK    \
		(0x000000ff << PP2_GMAC_LPI_CTRL_0_TS_LIMIT_OFFS)

/* Lpi Control 1 */
#define PP2_GMAC_LPI_CTRL_1_REG				(0x00c4)
#define PP2_GMAC_LPI_CTRL_1_LPI_REQUEST_EN_OFFS		0
#define PP2_GMAC_LPI_CTRL_1_LPI_REQUEST_EN_MASK    \
		(0x00000001 << PP2_GMAC_LPI_CTRL_1_LPI_REQUEST_EN_OFFS)

#define PP2_GMAC_LPI_CTRL_1_LPI_REQUEST_FORCE_OFFS		1
#define PP2_GMAC_LPI_CTRL_1_LPI_REQUEST_FORCE_MASK    \
		(0x00000001 << PP2_GMAC_LPI_CTRL_1_LPI_REQUEST_FORCE_OFFS)

#define PP2_GMAC_LPI_CTRL_1_LPI_MANUAL_MODE_OFFS		2
#define PP2_GMAC_LPI_CTRL_1_LPI_MANUAL_MODE_MASK    \
		(0x00000001 << PP2_GMAC_LPI_CTRL_1_LPI_MANUAL_MODE_OFFS)

#define PP2_GMAC_LPI_CTRL_1_EN_GTX_CLK_HALT_OFFS		3
#define PP2_GMAC_LPI_CTRL_1_EN_GTX_CLK_HALT_MASK    \
		(0x00000001 << PP2_GMAC_LPI_CTRL_1_EN_GTX_CLK_HALT_OFFS)

#define PP2_GMAC_LPI_CTRL_1_TW_LIMIT_OFFS		4
#define PP2_GMAC_LPI_CTRL_1_TW_LIMIT_MASK    \
		(0x00000fff << PP2_GMAC_LPI_CTRL_1_TW_LIMIT_OFFS)

/* Lpi Control 2 */
#define PP2_GMAC_LPI_CTRL_2_REG				(0x00c8)
#define PP2_GMAC_LPI_CTRL_2_LPI_CLK_DIV_OFFS		0
#define PP2_GMAC_LPI_CTRL_2_LPI_CLK_DIV_MASK    \
		(0x0000007f << PP2_GMAC_LPI_CTRL_2_LPI_CLK_DIV_OFFS)

#define PP2_GMAC_LPI_CTRL_2_PCS_RX_ER_MASK_DISABLE_OFFS		7
#define PP2_GMAC_LPI_CTRL_2_PCS_RX_ER_MASK_DISABLE_MASK    \
		(0x00000001 << PP2_GMAC_LPI_CTRL_2_PCS_RX_ER_MASK_DISABLE_OFFS)

#define PP2_GMAC_LPI_CTRL_2_EN_GMII2MII_LPI_FIX_OFFS		8
#define PP2_GMAC_LPI_CTRL_2_EN_GMII2MII_LPI_FIX_MASK    \
		(0x00000001 << PP2_GMAC_LPI_CTRL_2_EN_GMII2MII_LPI_FIX_OFFS)

/* Lpi Status */
#define PP2_GMAC_LPI_STATUS_REG				(0x00cc)
#define PP2_GMAC_LPI_STATUS_PCS_RX_LPI_STATUS_OFFS		0
#define PP2_GMAC_LPI_STATUS_PCS_RX_LPI_STATUS_MASK    \
		(0x00000001 << PP2_GMAC_LPI_STATUS_PCS_RX_LPI_STATUS_OFFS)

#define PP2_GMAC_LPI_STATUS_PCS_TX_LPI_STATUS_OFFS		1
#define PP2_GMAC_LPI_STATUS_PCS_TX_LPI_STATUS_MASK    \
		(0x00000001 << PP2_GMAC_LPI_STATUS_PCS_TX_LPI_STATUS_OFFS)

#define PP2_GMAC_LPI_STATUS_MAC_RX_LP_IDLE_STATUS_OFFS		2
#define PP2_GMAC_LPI_STATUS_MAC_RX_LP_IDLE_STATUS_MASK    \
		(0x00000001 << PP2_GMAC_LPI_STATUS_MAC_RX_LP_IDLE_STATUS_OFFS)

#define PP2_GMAC_LPI_STATUS_MAC_TX_LP_WAIT_STATUS_OFFS		3
#define PP2_GMAC_LPI_STATUS_MAC_TX_LP_WAIT_STATUS_MASK    \
		(0x00000001 << PP2_GMAC_LPI_STATUS_MAC_TX_LP_WAIT_STATUS_OFFS)

#define PP2_GMAC_LPI_STATUS_MAC_TX_LP_IDLE_STATUS_OFFS		4
#define PP2_GMAC_LPI_STATUS_MAC_TX_LP_IDLE_STATUS_MASK    \
		(0x00000001 << PP2_GMAC_LPI_STATUS_MAC_TX_LP_IDLE_STATUS_OFFS)

/* Lpi Counter */
#define PP2_GMAC_LPI_CNTR_REG				(0x00d0)
#define PP2_GMAC_LPI_CNTR_LPI_COUNTER_OFFS		0
#define PP2_GMAC_LPI_CNTR_LPI_COUNTER_MASK    \
		(0x0000ffff << PP2_GMAC_LPI_CNTR_LPI_COUNTER_OFFS)

/* Pulse 1 Ms Low */
#define PP2_GMAC_PULSE_1_MS_LOW_REG			(0x00d4)
#define PP2_GMAC_PULSE_1_MS_LOW_PULSE_1MS_MAX_LOW_OFFS		0
#define PP2_GMAC_PULSE_1_MS_LOW_PULSE_1MS_MAX_LOW_MASK    \
		(0x0000ffff << PP2_GMAC_PULSE_1_MS_LOW_PULSE_1MS_MAX_LOW_OFFS)

/* Pulse 1 Ms High */
#define PP2_GMAC_PULSE_1_MS_HIGH_REG			(0x00d8)
#define PP2_GMAC_PULSE_1_MS_HIGH_PULSE_1MS_MAX_HIGH_OFFS		0
#define PP2_GMAC_PULSE_1_MS_HIGH_PULSE_1MS_MAX_HIGH_MASK    \
		(0x0000ffff << PP2_GMAC_PULSE_1_MS_HIGH_PULSE_1MS_MAX_HIGH_OFFS)

/* Port Interrupt Cause */
#define PP2_GMAC_INTERRUPT_CAUSE_REG			(0x0020)
/* Port Interrupt Mask */
#define PP2_GMAC_INTERRUPT_MASK_REG			(0x0024)
#define PP2_GMAC_INTERRUPT_CAUSE_LINK_CHANGE_OFFS	1
#define PP2_GMAC_INTERRUPT_CAUSE_LINK_CHANGE_MASK	(0x1 << \
		PP2_GMAC_INTERRUPT_CAUSE_LINK_CHANGE_OFFS)

/* Port Interrupt Summary Cause */
#define PP2_GMAC_INTERRUPT_SUM_CAUSE_REG			(0x00A0)
/* Port Interrupt Summary Mask */
#define PP2_GMAC_INTERRUPT_SUM_MASK_REG			(0x00A4)
#define PP2_GMAC_INTERRUPT_SUM_CAUSE_LINK_CHANGE_OFFS	1
#define PP2_GMAC_INTERRUPT_SUM_CAUSE_LINK_CHANGE_MASK	(0x1 << \
		PP2_GMAC_INTERRUPT_SUM_CAUSE_LINK_CHANGE_OFFS)

/**************/
/* XLGMAC REGS  */
/**************/

/* Port Mac Control0 */
#define PP2_XLG_PORT_MAC_CTRL0_REG			(0x0000)
#define PP2_XLG_MAC_CTRL0_PORTEN_OFFS		0
#define PP2_XLG_MAC_CTRL0_PORTEN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL0_PORTEN_OFFS)

#define PP2_XLG_MAC_CTRL0_MACRESETN_OFFS		1
#define PP2_XLG_MAC_CTRL0_MACRESETN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL0_MACRESETN_OFFS)

#define PP2_XLG_MAC_CTRL0_FORCELINKDOWN_OFFS		2
#define PP2_XLG_MAC_CTRL0_FORCELINKDOWN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL0_FORCELINKDOWN_OFFS)

#define PP2_XLG_MAC_CTRL0_FORCELINKPASS_OFFS		3
#define PP2_XLG_MAC_CTRL0_FORCELINKPASS_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL0_FORCELINKPASS_OFFS)

#define PP2_XLG_MAC_CTRL0_TXIPGMODE_OFFS		5
#define PP2_XLG_MAC_CTRL0_TXIPGMODE_MASK    \
		(0x00000003 << PP2_XLG_MAC_CTRL0_TXIPGMODE_OFFS)

#define PP2_XLG_MAC_CTRL0_RXFCEN_OFFS		7
#define PP2_XLG_MAC_CTRL0_RXFCEN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL0_RXFCEN_OFFS)

#define PP2_XLG_MAC_CTRL0_TXFCEN_OFFS		8
#define PP2_XLG_MAC_CTRL0_TXFCEN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL0_TXFCEN_OFFS)

#define PP2_XLG_MAC_CTRL0_RXCRCCHECKEN_OFFS		9
#define PP2_XLG_MAC_CTRL0_RXCRCCHECKEN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL0_RXCRCCHECKEN_OFFS)

#define PP2_XLG_MAC_CTRL0_PERIODICXONEN_OFFS		10
#define PP2_XLG_MAC_CTRL0_PERIODICXONEN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL0_PERIODICXONEN_OFFS)

#define PP2_XLG_MAC_CTRL0_RXCRCSTRIPEN_OFFS		11
#define PP2_XLG_MAC_CTRL0_RXCRCSTRIPEN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL0_RXCRCSTRIPEN_OFFS)

#define PP2_XLG_MAC_CTRL0_PADDINGDIS_OFFS		13
#define PP2_XLG_MAC_CTRL0_PADDINGDIS_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL0_PADDINGDIS_OFFS)

#define PP2_XLG_MAC_CTRL0_MIBCNTDIS_OFFS		14
#define PP2_XLG_MAC_CTRL0_MIBCNTDIS_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL0_MIBCNTDIS_OFFS)

#define PP2_XLG_MAC_CTRL0_PFC_CASCADE_PORT_ENABLE_OFFS		15
#define PP2_XLG_MAC_CTRL0_PFC_CASCADE_PORT_ENABLE_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL0_PFC_CASCADE_PORT_ENABLE_OFFS)

/* Port Mac Control1 */
#define PP2_XLG_PORT_MAC_CTRL1_REG			(0x0004)
#define PP2_XLG_MAC_CTRL1_FRAMESIZELIMIT_OFFS		0
#define PP2_XLG_MAC_CTRL1_FRAMESIZELIMIT_MASK    \
		(0x00001fff << PP2_XLG_MAC_CTRL1_FRAMESIZELIMIT_OFFS)

#define PP2_XLG_MAC_CTRL1_MACLOOPBACKEN_OFFS		13
#define PP2_XLG_MAC_CTRL1_MACLOOPBACKEN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL1_MACLOOPBACKEN_OFFS)

#define PP2_XLG_MAC_CTRL1_XGMIILOOPBACKEN_OFFS		14
#define PP2_XLG_MAC_CTRL1_XGMIILOOPBACKEN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL1_XGMIILOOPBACKEN_OFFS)

#define PP2_XLG_MAC_CTRL1_LOOPBACKCLOCKSELECT_OFFS		15
#define PP2_XLG_MAC_CTRL1_LOOPBACKCLOCKSELECT_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL1_LOOPBACKCLOCKSELECT_OFFS)

/* Port Mac Control2 */
#define PP2_XLG_PORT_MAC_CTRL2_REG		(0x0008)
#define PP2_XLG_MAC_CTRL2_SALOW_7_0_OFFS		0
#define PP2_XLG_MAC_CTRL2_SALOW_7_0_MASK    \
		(0x000000ff << PP2_XLG_MAC_CTRL2_SALOW_7_0_OFFS)

#define PP2_XLG_MAC_CTRL2_UNIDIRECTIONALEN_OFFS		8
#define PP2_XLG_MAC_CTRL2_UNIDIRECTIONALEN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL2_UNIDIRECTIONALEN_OFFS)

#define PP2_XLG_MAC_CTRL2_FIXEDIPGBASE_OFFS		9
#define PP2_XLG_MAC_CTRL2_FIXEDIPGBASE_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL2_FIXEDIPGBASE_OFFS)

#define PP2_XLG_MAC_CTRL2_PERIODICXOFFEN_OFFS		10
#define PP2_XLG_MAC_CTRL2_PERIODICXOFFEN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL2_PERIODICXOFFEN_OFFS)

#define PP2_XLG_MAC_CTRL2_SIMPLEXMODEEN_OFFS		13
#define PP2_XLG_MAC_CTRL2_SIMPLEXMODEEN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL2_SIMPLEXMODEEN_OFFS)

#define PP2_XLG_MAC_CTRL2_FC_MODE_OFFS		14
#define PP2_XLG_MAC_CTRL2_FC_MODE_MASK    \
		(0x00000003 << PP2_XLG_MAC_CTRL2_FC_MODE_OFFS)

/* Port Status */
#define PP2_XLG_MAC_PORT_STATUS_REG		(0x000c)
#define PP2_XLG_MAC_PORT_STATUS_LINKSTATUS_OFFS		0
#define PP2_XLG_MAC_PORT_STATUS_LINKSTATUS_MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_STATUS_LINKSTATUS_OFFS)

#define PP2_XLG_MAC_PORT_STATUS_REMOTEFAULT_OFFS		1
#define PP2_XLG_MAC_PORT_STATUS_REMOTEFAULT_MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_STATUS_REMOTEFAULT_OFFS)

#define PP2_XLG_MAC_PORT_STATUS_LOCALFAULT_OFFS		2
#define PP2_XLG_MAC_PORT_STATUS_LOCALFAULT_MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_STATUS_LOCALFAULT_OFFS)

#define PP2_XLG_MAC_PORT_STATUS_LINKSTATUSCLEAN_OFFS		3
#define PP2_XLG_MAC_PORT_STATUS_LINKSTATUSCLEAN_MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_STATUS_LINKSTATUSCLEAN_OFFS)

#define PP2_XLG_MAC_PORT_STATUS_LOCALFAULTCLEAN_OFFS		4
#define PP2_XLG_MAC_PORT_STATUS_LOCALFAULTCLEAN_MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_STATUS_LOCALFAULTCLEAN_OFFS)

#define PP2_XLG_MAC_PORT_STATUS_REMOTEFAULTCLEAN_OFFS		5
#define PP2_XLG_MAC_PORT_STATUS_REMOTEFAULTCLEAN_MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_STATUS_REMOTEFAULTCLEAN_OFFS)

#define PP2_XLG_MAC_PORT_STATUS_PORTRXPAUSE_OFFS		6
#define PP2_XLG_MAC_PORT_STATUS_PORTRXPAUSE_MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_STATUS_PORTRXPAUSE_OFFS)

#define PP2_XLG_MAC_PORT_STATUS_PORTTXPAUSE_OFFS		7
#define PP2_XLG_MAC_PORT_STATUS_PORTTXPAUSE_MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_STATUS_PORTTXPAUSE_OFFS)

#define PP2_XLG_MAC_PORT_STATUS_PFC_SYNC_FIFO_FULL_OFFS		8
#define PP2_XLG_MAC_PORT_STATUS_PFC_SYNC_FIFO_FULL_MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_STATUS_PFC_SYNC_FIFO_FULL_OFFS)

/* Port Fifos Thresholds Configuration */
#define PP2_XLG_PORT_FIFOS_THRS_CFG_REG		(0x001)
#define PP2_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_OFFS		0
#define PP2_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_MASK    \
		(0x0000001f << PP2_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_OFFS)

#define PP2_XLG_MAC_PORT_FIFOS_THRS_CFG_TXFIFOSIZE_OFFS		5
#define PP2_XLG_MAC_PORT_FIFOS_THRS_CFG_TXFIFOSIZE_MASK    \
		(0x0000003f << PP2_XLG_MAC_PORT_FIFOS_THRS_CFG_TXFIFOSIZE_OFFS)

#define PP2_XLG_MAC_PORT_FIFOS_THRS_CFG_TXRDTHR_OFFS		11
#define PP2_XLG_MAC_PORT_FIFOS_THRS_CFG_TXRDTHR_MASK    \
		(0x0000001f << PP2_XLG_MAC_PORT_FIFOS_THRS_CFG_TXRDTHR_OFFS)

/* Port Mac Control3 */
#define PP2_XLG_PORT_MAC_CTRL3_REG			(0x001c)
#define PP2_XLG_MAC_CTRL3_BUFSIZE_OFFS		0
#define PP2_XLG_MAC_CTRL3_BUFSIZE_MASK    \
		(0x0000003f << PP2_XLG_MAC_CTRL3_BUFSIZE_OFFS)

#define PP2_XLG_MAC_CTRL3_XTRAIPG_OFFS		6
#define PP2_XLG_MAC_CTRL3_XTRAIPG_MASK    \
		(0x0000007f << PP2_XLG_MAC_CTRL3_XTRAIPG_OFFS)

#define PP2_XLG_MAC_CTRL3_MACMODESELECT_OFFS		13
#define PP2_XLG_MAC_CTRL3_MACMODESELECT_MASK    \
		(0x00000007 << PP2_XLG_MAC_CTRL3_MACMODESELECT_OFFS)

/* Port Per Prio Flow Control Status */
#define PP2_XLG_PORT_PER_PRIO_FLOW_CTRL_STATUS_REG      (0x0020)
#define PP2_XLG_MAC_PORT_PER_PRIO_FLOW_CTRL_STATUS_PRIONSTATUS_OFFS	0
#define PP2_XLG_MAC_PORT_PER_PRIO_FLOW_CTRL_STATUS_PRIONSTATUS_MASK    \
		(0x00000001 << \
		PP2_XLG_MAC_PORT_PER_PRIO_FLOW_CTRL_STATUS_PRIONSTATUS_OFFS)

/* Debug Bus Status */
#define PP2_XLG_DEBUG_BUS_STATUS_REG		(0x0024)
#define PP2_XLG_MAC_DEBUG_BUS_STATUS_DEBUG_BUS_OFFS		0
#define PP2_XLG_MAC_DEBUG_BUS_STATUS_DEBUG_BUS_MASK    \
		(0x0000ffff << PP2_XLG_MAC_DEBUG_BUS_STATUS_DEBUG_BUS_OFFS)

/* Port Metal Fix */
#define PP2_XLG_PORT_METAL_FIX_REG		(0x002c)
#define PP2_XLG_MAC_PORT_METAL_FIX_EN_EOP_IN_FIFO__OFFS		0
#define PP2_XLG_MAC_PORT_METAL_FIX_EN_EOP_IN_FIFO__MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_METAL_FIX_EN_EOP_IN_FIFO__OFFS)

#define PP2_XLG_MAC_PORT_METAL_FIX_EN_LTF_FIX__OFFS		1
#define PP2_XLG_MAC_PORT_METAL_FIX_EN_LTF_FIX__MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_METAL_FIX_EN_LTF_FIX__OFFS)

#define PP2_XLG_MAC_PORT_METAL_FIX_EN_HOLD_FIX__OFFS		2
#define PP2_XLG_MAC_PORT_METAL_FIX_EN_HOLD_FIX__MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_METAL_FIX_EN_HOLD_FIX__OFFS)

#define PP2_XLG_MAC_PORT_METAL_FIX_EN_LED_FIX__OFFS		3
#define PP2_XLG_MAC_PORT_METAL_FIX_EN_LED_FIX__MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_METAL_FIX_EN_LED_FIX__OFFS)

#define PP2_XLG_MAC_PORT_METAL_FIX_EN_PAD_PROTECT__OFFS		4
#define PP2_XLG_MAC_PORT_METAL_FIX_EN_PAD_PROTECT__MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_METAL_FIX_EN_PAD_PROTECT__OFFS)

#define PP2_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS44__OFFS		5
#define PP2_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS44__MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS44__OFFS)

#define PP2_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS42__OFFS		6
#define PP2_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS42__MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS42__OFFS)

#define PP2_XLG_MAC_PORT_METAL_FIX_EN_FLUSH_FIX_OFFS		7
#define PP2_XLG_MAC_PORT_METAL_FIX_EN_FLUSH_FIX_MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_METAL_FIX_EN_FLUSH_FIX_OFFS)

#define PP2_XLG_MAC_PORT_METAL_FIX_EN_PORT_EN_FIX_OFFS		8
#define PP2_XLG_MAC_PORT_METAL_FIX_EN_PORT_EN_FIX_MASK    \
		(0x00000001 << PP2_XLG_MAC_PORT_METAL_FIX_EN_PORT_EN_FIX_OFFS)

#define PP2_XLG_MAC_PORT_METAL_FIX_SPARE_DEF0_BITS_OFFS		9
#define PP2_XLG_MAC_PORT_METAL_FIX_SPARE_DEF0_BITS_MASK    \
		(0x0000000f << PP2_XLG_MAC_PORT_METAL_FIX_SPARE_DEF0_BITS_OFFS)

#define PP2_XLG_MAC_PORT_METAL_FIX_SPARE_DEF1_BITS_OFFS		13
#define PP2_XLG_MAC_PORT_METAL_FIX_SPARE_DEF1_BITS_MASK    \
		(0x00000007 << PP2_XLG_MAC_PORT_METAL_FIX_SPARE_DEF1_BITS_OFFS)

/* Xg Mib Counters Control */
#define PP2_XLG_MIB_CNTRS_CTRL_REG		(0x0030)
#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_XGCAPTURETRIGGER_OFFS		0
#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_XGCAPTURETRIGGER_MASK    \
		(0x00000001 << \
		PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_XGCAPTURETRIGGER_OFFS)

#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_XGDONTCLEARAFTERREAD_OFFS		1
#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_XGDONTCLEARAFTERREAD_MASK    \
		(0x00000001 << \
		PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_XGDONTCLEARAFTERREAD_OFFS)

#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_XGRXHISTOGRAMEN_OFFS		2
#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_XGRXHISTOGRAMEN_MASK    \
		(0x00000001 << \
		PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_XGRXHISTOGRAMEN_OFFS)

#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_XGTXHISTOGRAMEN_OFFS		3
#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_XGTXHISTOGRAMEN_MASK    \
		(0x00000001 << \
		PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_XGTXHISTOGRAMEN_OFFS)

#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE__OFFS	4
#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE__MASK    \
		(0x00000001 << \
		PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE__OFFS)

#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_LEDS_NUMBER_OFFS		5
#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_LEDS_NUMBER_MASK    \
		(0x0000003f << PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_LEDS_NUMBER_OFFS)

#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST_OFFS		11
#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST_MASK    \
		(0x00000001 << \
		PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST_OFFS)

#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522_OFFS		12
#define PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522_MASK    \
		(0x00000001 << \
		PP2_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522_OFFS)

/* Cn/ccfc Timer%i */
#define PP2_XLG_CNCCFC_TIMERI_REG(t)		((0x0038 + t * 4))
#define PP2_XLG_MAC_CNCCFC_TIMERI_PORTSPEEDTIMER_OFFS	0
#define PP2_XLG_MAC_CNCCFC_TIMERI_PORTSPEEDTIMER_MASK    \
		(0x0000ffff << PP2_XLG_MAC_CNCCFC_TIMERI_PORTSPEEDTIMER_OFFS)

/* Ppfc Control */
#define PP2_XLG_MAC_PPFC_CTRL_REG			(0x0060)
#define PP2_XLG_MAC_PPFC_CTRL_GLOBAL_PAUSE_ENI_OFFS		0
#define PP2_XLG_MAC_PPFC_CTRL_GLOBAL_PAUSE_ENI_MASK    \
		(0x00000001 << PP2_XLG_MAC_PPFC_CTRL_GLOBAL_PAUSE_ENI_OFFS)

#define PP2_XLG_MAC_PPFC_CTRL_DIP_BTS_677_EN_OFFS		9
#define PP2_XLG_MAC_PPFC_CTRL_DIP_BTS_677_EN_MASK    \
		(0x00000001 << PP2_XLG_MAC_PPFC_CTRL_DIP_BTS_677_EN_OFFS)

/* Fc Dsa Tag 0 */
#define PP2_XLG_MAC_FC_DSA_TAG_0_REG		(0x0068)
#define PP2_XLG_MAC_FC_DSA_TAG_0_DSATAGREG0_OFFS		0
#define PP2_XLG_MAC_FC_DSA_TAG_0_DSATAGREG0_MASK    \
		(0x0000ffff << PP2_XLG_MAC_FC_DSA_TAG_0_DSATAGREG0_OFFS)

/* Fc Dsa Tag 1 */
#define PP2_XLG_MAC_FC_DSA_TAG_1_REG		(0x006c)
#define PP2_XLG_MAC_FC_DSA_TAG_1_DSATAGREG1_OFFS		0
#define PP2_XLG_MAC_FC_DSA_TAG_1_DSATAGREG1_MASK    \
		(0x0000ffff << PP2_XLG_MAC_FC_DSA_TAG_1_DSATAGREG1_OFFS)

/* Fc Dsa Tag 2 */
#define PP2_XLG_MAC_FC_DSA_TAG_2_REG		(0x0070)
#define PP2_XLG_MAC_FC_DSA_TAG_2_DSATAGREG2_OFFS		0
#define PP2_XLG_MAC_FC_DSA_TAG_2_DSATAGREG2_MASK    \
		(0x0000ffff << PP2_XLG_MAC_FC_DSA_TAG_2_DSATAGREG2_OFFS)

/* Fc Dsa Tag 3 */
#define PP2_XLG_MAC_FC_DSA_TAG_3_REG		(0x0074)
#define PP2_XLG_MAC_FC_DSA_TAG_3_DSATAGREG3_OFFS		0
#define PP2_XLG_MAC_FC_DSA_TAG_3_DSATAGREG3_MASK    \
		(0x0000ffff << PP2_XLG_MAC_FC_DSA_TAG_3_DSATAGREG3_OFFS)

/* Dic Budget Compensation */
#define PP2_XLG_MAC_DIC_BUDGET_COMPENSATION_REG	(0x0080)
#define PP2_XLG_MAC_DIC_BUDGET_COMPENSATION_DIC_COUNTER_TO_ADD_8BYTES_OFFS 0
#define PP2_XLG_MAC_DIC_BUDGET_COMPENSATION_DIC_COUNTER_TO_ADD_8BYTES_MASK    \
		(0x0000ffff << \
	PP2_XLG_MAC_DIC_BUDGET_COMPENSATION_DIC_COUNTER_TO_ADD_8BYTES_OFFS)

/* Port Mac Control4 */
#define PP2_XLG_PORT_MAC_CTRL4_REG			(0x0084)
#define PP2_XLG_MAC_CTRL4_LLFC_GLOBAL_FC_ENABLE_OFFS		0
#define PP2_XLG_MAC_CTRL4_LLFC_GLOBAL_FC_ENABLE_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL4_LLFC_GLOBAL_FC_ENABLE_OFFS)

#define PP2_XLG_MAC_CTRL4_LED_STREAM_SELECT_OFFS		1
#define PP2_XLG_MAC_CTRL4_LED_STREAM_SELECT_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL4_LED_STREAM_SELECT_OFFS)

#define PP2_XLG_MAC_CTRL4_DEBUG_BUS_SELECT_OFFS		2
#define PP2_XLG_MAC_CTRL4_DEBUG_BUS_SELECT_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL4_DEBUG_BUS_SELECT_OFFS)

#define PP2_XLG_MAC_CTRL4_MASK_PCS_RESET_OFFS		3
#define PP2_XLG_MAC_CTRL4_MASK_PCS_RESET_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL4_MASK_PCS_RESET_OFFS)

#define PP2_XLG_MAC_CTRL4_ENABLE_SHORT_PREAMBLE_FOR_XLG_OFFS		4
#define PP2_XLG_MAC_CTRL4_ENABLE_SHORT_PREAMBLE_FOR_XLG_MASK    \
		(0x00000001 << \
		PP2_XLG_MAC_CTRL4_ENABLE_SHORT_PREAMBLE_FOR_XLG_OFFS)

#define PP2_XLG_MAC_CTRL4_FORWARD_802_3X_FC_EN_OFFS		5
#define PP2_XLG_MAC_CTRL4_FORWARD_802_3X_FC_EN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL4_FORWARD_802_3X_FC_EN_OFFS)

#define PP2_XLG_MAC_CTRL4_FORWARD_PFC_EN_OFFS		6
#define PP2_XLG_MAC_CTRL4_FORWARD_PFC_EN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL4_FORWARD_PFC_EN_OFFS)

#define PP2_XLG_MAC_CTRL4_FORWARD_UNKNOWN_FC_EN_OFFS		7
#define PP2_XLG_MAC_CTRL4_FORWARD_UNKNOWN_FC_EN_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL4_FORWARD_UNKNOWN_FC_EN_OFFS)

#define PP2_XLG_MAC_CTRL4_USE_XPCS_OFFS		8
#define PP2_XLG_MAC_CTRL4_USE_XPCS_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL4_USE_XPCS_OFFS)

#define PP2_XLG_MAC_CTRL4_DMA_INTERFACE_IS_64_BIT_OFFS		9
#define PP2_XLG_MAC_CTRL4_DMA_INTERFACE_IS_64_BIT_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL4_DMA_INTERFACE_IS_64_BIT_OFFS)

#define PP2_XLG_MAC_CTRL4_TX_DMA_INTERFACE_BITS_OFFS		10
#define PP2_XLG_MAC_CTRL4_TX_DMA_INTERFACE_BITS_MASK    \
		(0x00000003 << PP2_XLG_MAC_CTRL4_TX_DMA_INTERFACE_BITS_OFFS)

#define PP2_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_OFFS		12
#define PP2_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_MASK    \
		(0x00000001 << PP2_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_OFFS)

#define PP2_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK_OFFS    14
#define PP2_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK_MASK    \
	(0x00000001 << PP2_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK_OFFS)

/* Port Mac Control5 */
#define PP2_XLG_PORT_MAC_CTRL5_REG			(0x0088)
#define PP2_XLG_MAC_CTRL5_TXIPGLENGTH_OFFS		0
#define PP2_XLG_MAC_CTRL5_TXIPGLENGTH_MASK    \
		(0x0000000f << PP2_XLG_MAC_CTRL5_TXIPGLENGTH_OFFS)

#define PP2_XLG_MAC_CTRL5_PREAMBLELENGTHTX_OFFS		4
#define PP2_XLG_MAC_CTRL5_PREAMBLELENGTHTX_MASK    \
		(0x00000007 << PP2_XLG_MAC_CTRL5_PREAMBLELENGTHTX_OFFS)

#define PP2_XLG_MAC_CTRL5_PREAMBLELENGTHRX_OFFS		7
#define PP2_XLG_MAC_CTRL5_PREAMBLELENGTHRX_MASK    \
		(0x00000007 << PP2_XLG_MAC_CTRL5_PREAMBLELENGTHRX_OFFS)

#define PP2_XLG_MAC_CTRL5_TXNUMCRCBYTES_OFFS		10
#define PP2_XLG_MAC_CTRL5_TXNUMCRCBYTES_MASK    \
		(0x00000007 << PP2_XLG_MAC_CTRL5_TXNUMCRCBYTES_OFFS)

#define PP2_XLG_MAC_CTRL5_RXNUMCRCBYTES_OFFS		13
#define PP2_XLG_MAC_CTRL5_RXNUMCRCBYTES_MASK    \
		(0x00000007 << PP2_XLG_MAC_CTRL5_RXNUMCRCBYTES_OFFS)

/* External Control */
#define PP2_XLG_MAC_EXT_CTRL_REG			(0x0090)
#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL0_OFFS		0
#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL0_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL0_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL1_OFFS		1
#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL1_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL1_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL2_OFFS		2
#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL2_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL2_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL3_OFFS		3
#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL3_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL3_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL4_OFFS		4
#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL4_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL4_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL5_OFFS		5
#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL5_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL5_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL6_OFFS		6
#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL6_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL6_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL7_OFFS		7
#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL7_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL7_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL8_OFFS		8
#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL8_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL8_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL9_OFFS		9
#define PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL9_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL9_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_10_OFFS		10
#define PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_10_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_10_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_11_OFFS		11
#define PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_11_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_11_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_12_OFFS		12
#define PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_12_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_12_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_13_OFFS		13
#define PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_13_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_13_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_14_OFFS		14
#define PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_14_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_14_OFFS)

#define PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_15_OFFS		15
#define PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_15_MASK    \
		(0x00000001 << PP2_XLG_MAC_EXT_CTRL_EXT_CTRL_15_OFFS)

/* Macro Control */
#define PP2_XLG_MAC_MACRO_CTRL_REG			(0x0094)
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_0_OFFS		0
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_0_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_0_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_1_OFFS		1
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_1_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_1_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_2_OFFS		2
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_2_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_2_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_3_OFFS		3
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_3_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_3_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_4_OFFS		4
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_4_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_4_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_5_OFFS		5
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_5_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_5_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_6_OFFS		6
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_6_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_6_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_7_OFFS		7
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_7_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_7_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_8_OFFS		8
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_8_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_8_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_9_OFFS		9
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_9_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_9_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_10_OFFS		10
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_10_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_10_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_11_OFFS		11
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_11_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_11_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_12_OFFS		12
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_12_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_12_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_13_OFFS		13
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_13_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_13_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_14_OFFS		14
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_14_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_14_OFFS)

#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_15_OFFS		15
#define PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_15_MASK    \
		(0x00000001 << PP2_XLG_MAC_MACRO_CTRL_MACRO_CTRL_15_OFFS)

#define PP2_XLG_MAC_DIC_PPM_IPG_REDUCE_REG		(0x0094)

/* Port Interrupt Cause */
#define PP2_XLG_INTERRUPT_CAUSE_REG		(0x0014)
/* Port Interrupt Mask */
#define PP2_XLG_INTERRUPT_MASK_REG		(0x0018)
#define PP2_XLG_INTERRUPT_LINK_CHANGE_OFFS	1
#define PP2_XLG_INTERRUPT_LINK_CHANGE_MASK	(0x1 << \
		PP2_XLG_INTERRUPT_LINK_CHANGE_OFFS)

/* Port Interrupt Summary Cause */
#define PP2_XLG_EXTERNAL_INTERRUPT_CAUSE_REG	(0x0058)
/* Port Interrupt Summary Mask */
#define PP2_XLG_EXTERNAL_INTERRUPT_MASK_REG	(0x005C)
#define PP2_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_OFFS	1
#define PP2_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_MASK	(0x1 << \
		PP2_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_OFFS)

/***********/
/*XPCS REGS */
/***********/

/* Global Configuration 0 */
#define PP2_XPCS_GLOBAL_CFG_0_REG				(0x0)
#define PP2_XPCS_GLOBAL_CFG_0_PCSRESET_OFFS		0
#define PP2_XPCS_GLOBAL_CFG_0_PCSRESET_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_0_PCSRESET_OFFS)

#define PP2_XPCS_GLOBAL_CFG_0_DESKEWRESET_OFFS		1
#define PP2_XPCS_GLOBAL_CFG_0_DESKEWRESET_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_0_DESKEWRESET_OFFS)

#define PP2_XPCS_GLOBAL_CFG_0_TXRESET_OFFS		2
#define PP2_XPCS_GLOBAL_CFG_0_TXRESET_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_0_TXRESET_OFFS)

#define PP2_XPCS_GLOBAL_CFG_0_PCSMODE_OFFS		3
#define PP2_XPCS_GLOBAL_CFG_0_PCSMODE_MASK    \
		(0x00000003 << PP2_XPCS_GLOBAL_CFG_0_PCSMODE_OFFS)

#define PP2_XPCS_GLOBAL_CFG_0_LANEACTIVE_OFFS		5
#define PP2_XPCS_GLOBAL_CFG_0_LANEACTIVE_MASK    \
		(0x00000003 << PP2_XPCS_GLOBAL_CFG_0_LANEACTIVE_OFFS)

#define PP2_XPCS_GLOBAL_CFG_0_INDIVIDUALMODE_OFFS		7
#define PP2_XPCS_GLOBAL_CFG_0_INDIVIDUALMODE_MASK    \
		(0x0000003f << PP2_XPCS_GLOBAL_CFG_0_INDIVIDUALMODE_OFFS)

#define PP2_XPCS_GLOBAL_CFG_0_TXSMMODE_OFFS		13
#define PP2_XPCS_GLOBAL_CFG_0_TXSMMODE_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_0_TXSMMODE_OFFS)

#define PP2_XPCS_GLOBAL_CFG_0_TXSMIDLECNTDISABLE_OFFS		14
#define PP2_XPCS_GLOBAL_CFG_0_TXSMIDLECNTDISABLE_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_0_TXSMIDLECNTDISABLE_OFFS)

#define PP2_XPCS_GLOBAL_CFG_0_COMMADETCT2NDSYNCSMEN_OFFS		15
#define PP2_XPCS_GLOBAL_CFG_0_COMMADETCT2NDSYNCSMEN_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_0_COMMADETCT2NDSYNCSMEN_OFFS)

/* Global Configuration 1 */
#define PP2_XPCS_GLOBAL_CFG_1_REG				(0x4)
#define PP2_XPCS_GLOBAL_CFG_1_MACLOOPBACKEN_OFFS		0
#define PP2_XPCS_GLOBAL_CFG_1_MACLOOPBACKEN_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_1_MACLOOPBACKEN_OFFS)

#define PP2_XPCS_GLOBAL_CFG_1_PCSLOOPBACKEN_OFFS		1
#define PP2_XPCS_GLOBAL_CFG_1_PCSLOOPBACKEN_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_1_PCSLOOPBACKEN_OFFS)

#define PP2_XPCS_GLOBAL_CFG_1_REPEATERMODEEN_OFFS		2
#define PP2_XPCS_GLOBAL_CFG_1_REPEATERMODEEN_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_1_REPEATERMODEEN_OFFS)

#define PP2_XPCS_GLOBAL_CFG_1_LOOPBACKCLKSEL_OFFS		3
#define PP2_XPCS_GLOBAL_CFG_1_LOOPBACKCLKSEL_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_1_LOOPBACKCLKSEL_OFFS)

#define PP2_XPCS_GLOBAL_CFG_1_DESKEWCLKSEL_OFFS		4
#define PP2_XPCS_GLOBAL_CFG_1_DESKEWCLKSEL_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_1_DESKEWCLKSEL_OFFS)

#define PP2_XPCS_GLOBAL_CFG_1_TXSMREPEATERMODE_OFFS		5
#define PP2_XPCS_GLOBAL_CFG_1_TXSMREPEATERMODE_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_1_TXSMREPEATERMODE_OFFS)

#define PP2_XPCS_GLOBAL_CFG_1_RXLOCKBYPASSEN_OFFS		6
#define PP2_XPCS_GLOBAL_CFG_1_RXLOCKBYPASSEN_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_1_RXLOCKBYPASSEN_OFFS)

#define PP2_XPCS_GLOBAL_CFG_1_TXLOCKBYPASSEN_OFFS		7
#define PP2_XPCS_GLOBAL_CFG_1_TXLOCKBYPASSEN_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_1_TXLOCKBYPASSEN_OFFS)

#define PP2_XPCS_GLOBAL_CFG_1_REMOTEFAULTDIS_OFFS		8
#define PP2_XPCS_GLOBAL_CFG_1_REMOTEFAULTDIS_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_1_REMOTEFAULTDIS_OFFS)

#define PP2_XPCS_GLOBAL_CFG_1_SIGNALDETDOWNLOCALFAULTGENDIS_OFFS		9
#define PP2_XPCS_GLOBAL_CFG_1_SIGNALDETDOWNLOCALFAULTGENDIS_MASK    \
		(0x00000001 << \
		PP2_XPCS_GLOBAL_CFG_1_SIGNALDETDOWNLOCALFAULTGENDIS_OFFS)

#define PP2_XPCS_GLOBAL_CFG_1_CJPATGENEN_OFFS		10
#define PP2_XPCS_GLOBAL_CFG_1_CJPATGENEN_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_1_CJPATGENEN_OFFS)

#define PP2_XPCS_GLOBAL_CFG_1_CRPATGENEN_OFFS		11
#define PP2_XPCS_GLOBAL_CFG_1_CRPATGENEN_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_1_CRPATGENEN_OFFS)

#define PP2_XPCS_GLOBAL_CFG_1_CJRFORCEDISPEN_OFFS		12
#define PP2_XPCS_GLOBAL_CFG_1_CJRFORCEDISPEN_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_CFG_1_CJRFORCEDISPEN_OFFS)

/* Global Fifo Threshold Configuration */
#define PP2_XPCS_GLOBAL_FIFO_THR_CFG_REG				(0x8)
#define PP2_XPCS_GLOBAL_FIFO_THR_CFG_DESKEWTIMEOUTLIMIT_OFFS		0
#define PP2_XPCS_GLOBAL_FIFO_THR_CFG_DESKEWTIMEOUTLIMIT_MASK    \
		(0x0000000f << \
		PP2_XPCS_GLOBAL_FIFO_THR_CFG_DESKEWTIMEOUTLIMIT_OFFS)

#define PP2_XPCS_GLOBAL_FIFO_THR_CFG_DESKEWFIFOWRADDRFIX_OFFS		4
#define PP2_XPCS_GLOBAL_FIFO_THR_CFG_DESKEWFIFOWRADDRFIX_MASK    \
		(0x0000001f << \
		PP2_XPCS_GLOBAL_FIFO_THR_CFG_DESKEWFIFOWRADDRFIX_OFFS)

#define PP2_XPCS_GLOBAL_FIFO_THR_CFG_DESKEWFIFORDTH_OFFS		9
#define PP2_XPCS_GLOBAL_FIFO_THR_CFG_DESKEWFIFORDTH_MASK    \
		(0x0000000f << PP2_XPCS_GLOBAL_FIFO_THR_CFG_DESKEWFIFORDTH_OFFS)

#define PP2_XPCS_GLOBAL_FIFO_THR_CFG_PPMFIFORDTH_OFFS		13
#define PP2_XPCS_GLOBAL_FIFO_THR_CFG_PPMFIFORDTH_MASK    \
		(0x00000007 << PP2_XPCS_GLOBAL_FIFO_THR_CFG_PPMFIFORDTH_OFFS)

#define PP2_XPCS_GLOBAL_FIFO_THR_CFG_PPMFIFOEXTRAIDLECHKDIS_OFFS		16
#define PP2_XPCS_GLOBAL_FIFO_THR_CFG_PPMFIFOEXTRAIDLECHKDIS_MASK    \
		(0x00000001 << \
		PP2_XPCS_GLOBAL_FIFO_THR_CFG_PPMFIFOEXTRAIDLECHKDIS_OFFS)

/* Global Max Idle Counter */
#define PP2_XPCS_GLOBAL_MAX_IDLE_CNTR_REG			(0xc)
#define PP2_XPCS_GLOBAL_MAX_IDLE_CNTR_MAXIDLECNT_OFFS		0
#define PP2_XPCS_GLOBAL_MAX_IDLE_CNTR_MAXIDLECNT_MASK    \
		(0x0000ffff << PP2_XPCS_GLOBAL_MAX_IDLE_CNTR_MAXIDLECNT_OFFS)

/* Global Status */
#define PP2_XPCS_GLOBAL_STATUS_REG				(0x10)
#define PP2_XPCS_GLOBAL_STATUS_LINKUP_OFFS		0
#define PP2_XPCS_GLOBAL_STATUS_LINKUP_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_STATUS_LINKUP_OFFS)

#define PP2_XPCS_GLOBAL_STATUS_DESKEWACQUIRED_OFFS		1
#define PP2_XPCS_GLOBAL_STATUS_DESKEWACQUIRED_MASK    \
		(0x00000001 << PP2_XPCS_GLOBAL_STATUS_DESKEWACQUIRED_OFFS)

/* Global Deskew Error Counter */
#define PP2_XPCS_GLOBAL_DESKEW_ERR_CNTR_REG			(0x20)
#define PP2_XPCS_GLOBAL_DESKEW_ERR_CNTR_DESKEWERRCNT_OFFS		0
#define PP2_XPCS_GLOBAL_DESKEW_ERR_CNTR_DESKEWERRCNT_MASK    \
		(0x0000ffff << PP2_XPCS_GLOBAL_DESKEW_ERR_CNTR_DESKEWERRCNT_OFFS)

/* Tx Packets Counter LSB */
#define PP2_XPCS_TX_PCKTS_CNTR_LSB_REG				(0x30)
#define PP2_XPCS_TX_PCKTS_CNTR_LSB_TXPCKTCNTRLSB_OFFS		0
#define PP2_XPCS_TX_PCKTS_CNTR_LSB_TXPCKTCNTRLSB_MASK    \
		(0x0000ffff << PP2_XPCS_TX_PCKTS_CNTR_LSB_TXPCKTCNTRLSB_OFFS)

/* Tx Packets Counter MSB */
#define PP2_XPCS_TX_PCKTS_CNTR_MSB_REG				(0x34)
#define PP2_XPCS_TX_PCKTS_CNTR_MSB_TXPCKTCNTRMSB_OFFS		0
#define PP2_XPCS_TX_PCKTS_CNTR_MSB_TXPCKTCNTRMSB_MASK    \
		(0x0000ffff << PP2_XPCS_TX_PCKTS_CNTR_MSB_TXPCKTCNTRMSB_OFFS)

/* XPCS per Lane registers */

/* Lane Configuration 0 */
#define PP2_XPCS_LANE_CFG_0_REG				(0x50)
#define PP2_XPCS_LANE_CFG_0_TXRESETIND_OFFS		0
#define PP2_XPCS_LANE_CFG_0_TXRESETIND_MASK    \
		(0x00000001 << PP2_XPCS_LANE_CFG_0_TXRESETIND_OFFS)

#define PP2_XPCS_LANE_CFG_0_RXRESETIND_OFFS		1
#define PP2_XPCS_LANE_CFG_0_RXRESETIND_MASK    \
		(0x00000001 << PP2_XPCS_LANE_CFG_0_RXRESETIND_OFFS)

#define PP2_XPCS_LANE_CFG_0_INDIVIDUALLOOPBACK_OFFS		2
#define PP2_XPCS_LANE_CFG_0_INDIVIDUALLOOPBACK_MASK    \
		(0x00000001 << PP2_XPCS_LANE_CFG_0_INDIVIDUALLOOPBACK_OFFS)

#define PP2_XPCS_LANE_CFG_0_INDIVIDUALLINELOOPBACK_OFFS		3
#define PP2_XPCS_LANE_CFG_0_INDIVIDUALLINELOOPBACK_MASK    \
		(0x00000001 << PP2_XPCS_LANE_CFG_0_INDIVIDUALLINELOOPBACK_OFFS)

#define PP2_XPCS_LANE_CFG_0_TXSMBYPASSEN_OFFS		4
#define PP2_XPCS_LANE_CFG_0_TXSMBYPASSEN_MASK    \
		(0x00000001 << PP2_XPCS_LANE_CFG_0_TXSMBYPASSEN_OFFS)

#define PP2_XPCS_LANE_CFG_0_RXIDLEGENBYPASSEN_OFFS		5
#define PP2_XPCS_LANE_CFG_0_RXIDLEGENBYPASSEN_MASK    \
		(0x00000001 << PP2_XPCS_LANE_CFG_0_RXIDLEGENBYPASSEN_OFFS)

#define PP2_XPCS_LANE_CFG_0_SIGNALDETECTBYPASSEN_OFFS		6
#define PP2_XPCS_LANE_CFG_0_SIGNALDETECTBYPASSEN_MASK    \
		(0x00000001 << PP2_XPCS_LANE_CFG_0_SIGNALDETECTBYPASSEN_OFFS)

#define PP2_XPCS_LANE_CFG_0_CJPATCHKEN_OFFS		7
#define PP2_XPCS_LANE_CFG_0_CJPATCHKEN_MASK    \
		(0x00000001 << PP2_XPCS_LANE_CFG_0_CJPATCHKEN_OFFS)

#define PP2_XPCS_LANE_CFG_0_CRPATCHKEN_OFFS		8
#define PP2_XPCS_LANE_CFG_0_CRPATCHKEN_MASK    \
		(0x00000001 << PP2_XPCS_LANE_CFG_0_CRPATCHKEN_OFFS)

#define PP2_XPCS_LANE_CFG_0_PRBSCHECKEN_OFFS		11
#define PP2_XPCS_LANE_CFG_0_PRBSCHECKEN_MASK    \
		(0x00000001 << PP2_XPCS_LANE_CFG_0_PRBSCHECKEN_OFFS)

#define PP2_XPCS_LANE_CFG_0_TESTGENEN_OFFS		12
#define PP2_XPCS_LANE_CFG_0_TESTGENEN_MASK    \
		(0x00000001 << PP2_XPCS_LANE_CFG_0_TESTGENEN_OFFS)

#define PP2_XPCS_LANE_CFG_0_TESTMODE_OFFS		13
#define PP2_XPCS_LANE_CFG_0_TESTMODE_MASK    \
		(0x00000003 << PP2_XPCS_LANE_CFG_0_TESTMODE_OFFS)

#define PP2_XPCS_LANE_CFG_0_TESTMODEEN_OFFS		15
#define PP2_XPCS_LANE_CFG_0_TESTMODEEN_MASK    \
		(0x00000001 << PP2_XPCS_LANE_CFG_0_TESTMODEEN_OFFS)

/* Lane Configuration 1 */
#define PP2_XPCS_LANE_CFG_1_REG				(0x54)
#define PP2_XPCS_LANE_CFG_1_LED0CTRL_OFFS		0
#define PP2_XPCS_LANE_CFG_1_LED0CTRL_MASK    \
		(0x0000000f << PP2_XPCS_LANE_CFG_1_LED0CTRL_OFFS)

#define PP2_XPCS_LANE_CFG_1_LED1CTRL_OFFS		4
#define PP2_XPCS_LANE_CFG_1_LED1CTRL_MASK    \
		(0x0000000f << PP2_XPCS_LANE_CFG_1_LED1CTRL_OFFS)

#define PP2_XPCS_LANE_CFG_1_TXSWPSEL_OFFS		8
#define PP2_XPCS_LANE_CFG_1_TXSWPSEL_MASK    \
		(0x00000007 << PP2_XPCS_LANE_CFG_1_TXSWPSEL_OFFS)

#define PP2_XPCS_LANE_CFG_1_RXSWPSEL_OFFS		11
#define PP2_XPCS_LANE_CFG_1_RXSWPSEL_MASK    \
		(0x00000007 << PP2_XPCS_LANE_CFG_1_RXSWPSEL_OFFS)

/* Lane Status */
#define PP2_XPCS_LANE_STATUS_REG				(0x5c)
#define PP2_XPCS_LANE_STATUS_PRBSCHECKLOCKED_OFFS		0
#define PP2_XPCS_LANE_STATUS_PRBSCHECKLOCKED_MASK    \
		(0x00000001 << PP2_XPCS_LANE_STATUS_PRBSCHECKLOCKED_OFFS)

#define PP2_XPCS_LANE_STATUS_PLLLOCKED_OFFS		1
#define PP2_XPCS_LANE_STATUS_PLLLOCKED_MASK    \
		(0x00000001 << PP2_XPCS_LANE_STATUS_PLLLOCKED_OFFS)

#define PP2_XPCS_LANE_STATUS_SIGNALDETECTED_OFFS		2
#define PP2_XPCS_LANE_STATUS_SIGNALDETECTED_MASK    \
		(0x00000001 << PP2_XPCS_LANE_STATUS_SIGNALDETECTED_OFFS)

#define PP2_XPCS_LANE_STATUS_COMMADETECTED_OFFS		3
#define PP2_XPCS_LANE_STATUS_COMMADETECTED_MASK    \
		(0x00000001 << PP2_XPCS_LANE_STATUS_COMMADETECTED_OFFS)

#define PP2_XPCS_LANE_STATUS_SYNCOK_OFFS		4
#define PP2_XPCS_LANE_STATUS_SYNCOK_MASK    \
		(0x00000001 << PP2_XPCS_LANE_STATUS_SYNCOK_OFFS)

/* Symbol Error Counter */
#define PP2_XPCS_SYMBOL_ERR_CNTR_REG			(0x68)
#define PP2_XPCS_SYMBOL_ERR_CNTR_SYMBOLERRCNT_OFFS	0
#define PP2_XPCS_SYMBOL_ERR_CNTR_SYMBOLERRCNT_MASK    \
		(0x0000ffff << PP2_XPCS_SYMBOL_ERR_CNTR_SYMBOLERRCNT_OFFS)

/* Disparity Error Counter */
#define PP2_XPCS_DISPARITY_ERR_CNTR_REG			(0x6c)
#define PP2_XPCS_DISPARITY_ERR_CNTR_DISPARITYERRCNT_OFFS		0
#define PP2_XPCS_DISPARITY_ERR_CNTR_DISPARITYERRCNT_MASK    \
		(0x0000ffff << PP2_XPCS_DISPARITY_ERR_CNTR_DISPARITYERRCNT_OFFS)

/* Prbs Error Counter */
#define PP2_XPCS_PRBS_ERR_CNTR_REG			(0x70)
#define PP2_XPCS_PRBS_ERR_CNTR_PRBSERRCNT_OFFS		0
#define PP2_XPCS_PRBS_ERR_CNTR_PRBSERRCNT_MASK    \
		(0x0000ffff << PP2_XPCS_PRBS_ERR_CNTR_PRBSERRCNT_OFFS)

/* Rx Packets Counter LSB */
#define PP2_XPCS_RX_PCKTS_CNTR_LSB_REG			(0x74)
#define PP2_XPCS_RX_PCKTS_CNTR_LSB_RXPCKTCNTRLSB_OFFS		0
#define PP2_XPCS_RX_PCKTS_CNTR_LSB_RXPCKTCNTRLSB_MASK    \
		(0x0000ffff << PP2_XPCS_RX_PCKTS_CNTR_LSB_RXPCKTCNTRLSB_OFFS)

/* Rx Packets Counter MSB */
#define PP2_XPCS_RX_PCKTS_CNTR_MSB_REG			(0x78)
#define PP2_XPCS_RX_PCKTS_CNTR_MSB_RXPCKTCNTRMSB_OFFS	0
#define PP2_XPCS_RX_PCKTS_CNTR_MSB_RXPCKTCNTRMSB_MASK    \
		(0x0000ffff << PP2_XPCS_RX_PCKTS_CNTR_MSB_RXPCKTCNTRMSB_OFFS)

/* Rx Bad Packets Counter LSB */
#define PP2_XPCS_RX_BAD_PCKTS_CNTR_LSB_REG			(0x7c)
#define PP2_XPCS_RX_BAD_PCKTS_CNTR_LSB_RXBADPCKTCNTRLSB_OFFS		0
#define PP2_XPCS_RX_BAD_PCKTS_CNTR_LSB_RXBADPCKTCNTRLSB_MASK    \
		(0x0000ffff << \
		PP2_XPCS_RX_BAD_PCKTS_CNTR_LSB_RXBADPCKTCNTRLSB_OFFS)

/* Rx Bad Packets Counter MSB */
#define PP2_XPCS_RX_BAD_PCKTS_CNTR_MSB_REG			(0x80)
#define PP2_XPCS_RX_BAD_PCKTS_CNTR_MSB_RXBADPCKTCNTRMSB_OFFS		0
#define PP2_XPCS_RX_BAD_PCKTS_CNTR_MSB_RXBADPCKTCNTRMSB_MASK    \
		(0x0000ffff << \
		PP2_XPCS_RX_BAD_PCKTS_CNTR_MSB_RXBADPCKTCNTRMSB_OFFS)

/* Cyclic Data 0 */
#define PP2_XPCS_CYCLIC_DATA_0_REG				(0x84)
#define PP2_XPCS_CYCLIC_DATA_0_CYCLICDATA0_OFFS		0
#define PP2_XPCS_CYCLIC_DATA_0_CYCLICDATA0_MASK    \
		(0x000003ff << PP2_XPCS_CYCLIC_DATA_0_CYCLICDATA0_OFFS)

/* Cyclic Data 1 */
#define PP2_XPCS_CYCLIC_DATA_1_REG				(0x88)
#define PP2_XPCS_CYCLIC_DATA_1_CYCLICDATA1_OFFS		0
#define PP2_XPCS_CYCLIC_DATA_1_CYCLICDATA1_MASK    \
		(0x000003ff << PP2_XPCS_CYCLIC_DATA_1_CYCLICDATA1_OFFS)

/* Cyclic Data 2 */
#define PP2_XPCS_CYCLIC_DATA_2_REG				(0x8c)
#define PP2_XPCS_CYCLIC_DATA_2_CYCLICDATA2_OFFS		0
#define PP2_XPCS_CYCLIC_DATA_2_CYCLICDATA2_MASK    \
		(0x000003ff << PP2_XPCS_CYCLIC_DATA_2_CYCLICDATA2_OFFS)

/* Cyclic Data 3 */
#define PP2_XPCS_CYCLIC_DATA_3_REG				(0x90)
#define PP2_XPCS_CYCLIC_DATA_3_CYCLICDATA3_OFFS		0
#define PP2_XPCS_CYCLIC_DATA_3_CYCLICDATA3_MASK    \
		(0x000003ff << PP2_XPCS_CYCLIC_DATA_3_CYCLICDATA3_OFFS)

/*************/
/*SERDES REGS  */
/*************/

#define PP2_SERDES_CFG_0_REG			(0x00)

#define PP2_SERDES_CFG_0_PU_PLL_OFFS		1
#define PP2_SERDES_CFG_0_PU_PLL_MASK		(0x00000001 << \
			PP2_SERDES_CFG_0_PU_PLL_OFFS)
#define PP2_SERDES_CFG_0_RX_PLL_OFFS		11
#define PP2_SERDES_CFG_0_RX_PLL_MASK		(0x00000001 << \
			PP2_SERDES_CFG_0_RX_PLL_OFFS)
#define PP2_SERDES_CFG_0_TX_PLL_OFFS		12
#define PP2_SERDES_CFG_0_TX_PLL_MASK		(0x00000001 << \
			PP2_SERDES_CFG_0_TX_PLL_OFFS)
#define PP2_SERDES_CFG_0_MEDIA_MODE_OFFS		15
#define PP2_SERDES_CFG_0_MEDIA_MODE_MASK		(0x00000001 << \
			PP2_SERDES_CFG_0_MEDIA_MODE_OFFS)

#define PP2_SERDES_CFG_1_REG			(0x04)
#define PP2_SERDES_CFG_1_ANALOG_RESET_OFFS	3
#define PP2_SERDES_CFG_1_ANALOG_RESET_MASK    \
		(0x00000001 << PP2_SERDES_CFG_1_ANALOG_RESET_OFFS)

#define PP2_SERDES_CFG_1_CORE_RESET_OFFS		5
#define PP2_SERDES_CFG_1_CORE_RESET_MASK    \
		(0x00000001 << PP2_SERDES_CFG_1_CORE_RESET_OFFS)

#define PP2_SERDES_CFG_1_DIGITAL_RESET_OFFS	6
#define PP2_SERDES_CFG_1_DIGITAL_RESET_MASK    \
		(0x00000001 << PP2_SERDES_CFG_1_DIGITAL_RESET_OFFS)

#define PP2_SERDES_CFG_1_TX_SYNC_EN_OFFS		7
#define PP2_SERDES_CFG_1_TX_SYNC_EN_MASK    \
		(0x00000001 << PP2_SERDES_CFG_1_TX_SYNC_EN_OFFS)

#define PP2_SERDES_CFG_2_REG			(0x08)
#define PP2_SERDES_CFG_3_REG			(0x0c)
#define PP2_SERDES_MISC_REG			(0x14)

/*************/
/*SMI  REGS      */
/*************/

#define PP2_SMI_MANAGEMENT_BUSY_OFFS					28
#define PP2_SMI_MANAGEMENT_BUSY_MASK					\
	(0x1 << PP2_SMI_MANAGEMENT_BUSY_OFFS)
#define PP2_SMI_MANAGEMENT_READ_VALID_OFFS				27
#define PP2_SMI_MANAGEMENT_READ_VALID_MASK				\
	(0x1 << PP2_SMI_MANAGEMENT_READ_VALID_OFFS)
#define PP2_SMI_MANAGEMENT_OPCODE_OFFS					26
#define PP2_SMI_MANAGEMENT_OPCODE_MASK					\
	(0x1 << PP2_SMI_MANAGEMENT_OPCODE_OFFS)
#define PP2_SMI_MANAGEMENT_REGAD_OFFS					21
#define PP2_SMI_MANAGEMENT_REGAD_MASK					\
	(0x1F << PP2_SMI_MANAGEMENT_REGAD_OFFS)
#define PP2_SMI_MANAGEMENT_PHYAD_OFFS					16
#define PP2_SMI_MANAGEMENT_PHYAD_MASK					\
	(0x1F << PP2_SMI_MANAGEMENT_PHYAD_OFFS)
#define PP2_SMI_MANAGEMENT_DATA_OFFS					0
#define PP2_SMI_MANAGEMENT_DATA_MASK					\
	(0xFFFF << PP2_SMI_MANAGEMENT_DATA_OFFS)

/* SMI_MISC_CFG Register */
#define PP2_SMI_MISC_CFG_REG						(0x4)

#define PP2_SMI_MISC_CFG_SMI_ACCELERATE_OFFS				0
#define PP2_SMI_MISC_CFG_SMI_ACCELERATE_MASK				\
	(0x1 << PP2_SMI_MISC_CFG_SMI_ACCELERATE_OFFS)
#define PP2_SMI_MISC_CFG_SMI_FASTMDC_OFFS				1
#define PP2_SMI_MISC_CFG_SMI_FASTMDC_MASK				\
	(0x1 << PP2_SMI_MISC_CFG_SMI_FASTMDC_OFFS)
#define PP2_SMI_MISC_CFG_FAST_MDC_DIVISION_SELECTOR_OFFS			2
#define PP2_SMI_MISC_CFG_FAST_MDC_DIVISION_SELECTOR_MASK			\
	(0x3 << PP2_SMI_MISC_CFG_FAST_MDC_DIVISION_SELECTOR_OFFS)
#define PP2_SMI_MISC_CFG_ENABLE_MDIO_OUT_LATENCY_OFFS			4
#define PP2_SMI_MISC_CFG_ENABLE_MDIO_OUT_LATENCY_MASK			\
	(0x1 << PP2_SMI_MISC_CFG_ENABLE_MDIO_OUT_LATENCY_OFFS)
#define PP2_SMI_MISC_CFG_AUTOPOLLNUMOFPORTS_OFFS				5
#define PP2_SMI_MISC_CFG_AUTOPOLLNUMOFPORTS_MASK				\
	(0x1F << PP2_SMI_MISC_CFG_AUTOPOLLNUMOFPORTS_OFFS)
#define PP2_SMI_MISC_CFG_ENABLE_POLLING_OFFS				10
#define PP2_SMI_MISC_CFG_ENABLE_POLLING_MASK				\
	(0x1 << PP2_SMI_MISC_CFG_ENABLE_POLLING_OFFS)
#define PP2_SMI_MISC_CFG_INVERT_MDC_OFFS					11
#define PP2_SMI_MISC_CFG_INVERT_MDC_MASK					\
	(0x1 << PP2_SMI_MISC_CFG_INVERT_MDC_OFFS)

/* PHY_AN_CFG Register */
#define PP2_SMI_PHY_AN_CFG_REG						(0x8)

#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT0_OFFS			0
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT0_MASK			\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT0_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT1_OFFS			1
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT1_MASK			\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT1_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT2_OFFS			2
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT2_MASK			\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT2_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT3_OFFS			3
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT3_MASK			\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT3_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT4_OFFS			4
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT4_MASK			\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT4_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT5_OFFS			5
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT5_MASK			\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT5_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT6_OFFS			6
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT6_MASK			\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT6_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT7_OFFS			7
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT7_MASK			\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT7_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT8_OFFS			8
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT8_MASK			\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT8_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT9_OFFS			9
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT9_MASK			\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT9_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT10_OFFS		10
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT10_MASK		\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT10_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT11_OFFS		11
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT11_MASK		\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT11_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT12_OFFS		12
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT12_MASK		\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT12_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT13_OFFS		13
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT13_MASK		\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT13_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT14_OFFS		14
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT14_MASK		\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT14_OFFS)
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT15_OFFS		15
#define PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT15_MASK		\
	(0x1 << PP2_SMI_PHY_AN_CFG_AUTOMEDIA_SELECTEN_PORT15_OFFS)
#define PP2_SMI_PHY_AN_CFG_SKIPSWRESET_SMI_OFFS				16
#define PP2_SMI_PHY_AN_CFG_SKIPSWRESET_SMI_MASK				\
	(0x1 << PP2_SMI_PHY_AN_CFG_SKIPSWRESET_SMI_OFFS)
#define PP2_SMI_PHY_AN_CFG_STOP_AUTONEGSMI_OFFS				17
#define PP2_SMI_PHY_AN_CFG_STOP_AUTONEGSMI_MASK				\
	(0x1 << PP2_SMI_PHY_AN_CFG_STOP_AUTONEGSMI_OFFS)
#define PP2_SMI_PHY_AN_CFG_MASTERSMI_OFFS				18
#define PP2_SMI_PHY_AN_CFG_MASTERSMI_MASK				\
	(0x1 << PP2_SMI_PHY_AN_CFG_MASTERSMI_OFFS)
#define PP2_SMI_PHY_AN_CFG_SGMIIINBANDFCEN_OFFS				19
#define PP2_SMI_PHY_AN_CFG_SGMIIINBANDFCEN_MASK				\
	(0x1 << PP2_SMI_PHY_AN_CFG_SGMIIINBANDFCEN_OFFS)
#define PP2_SMI_PHY_AN_CFG_FCADVSETFIBER_OFFS				20
#define PP2_SMI_PHY_AN_CFG_FCADVSETFIBER_MASK				\
	(0x1 << PP2_SMI_PHY_AN_CFG_FCADVSETFIBER_OFFS)

/* PHY_ADDRESS_REGISTER0 Register */
#define PP2_SMI_PHY_ADDRESS_REG(n)				(0xC + 0x4 * n)
#define PP2_SMI_PHY_ADDRESS_PHYAD_OFFS					0
#define PP2_SMI_PHY_ADDRESS_PHYAD_MASK					\
	(0x1F << PP2_SMI_PHY_ADDRESS_PHYAD_OFFS)

/*************/
/*   MIB  REGS    */
/*************/

/* GMAC_MIB Counters register definitions */
#define PP2_MIB_GOOD_OCTETS_RECEIVED_LOW		0x0
#define PP2_MIB_GOOD_OCTETS_RECEIVED_HIGH	0x4
#define PP2_MIB_BAD_OCTETS_RECEIVED		0x8
#define PP2_MIB_CRC_ERRORS_SENT			0xc
#define PP2_MIB_UNICAST_FRAMES_RECEIVED		0x10
/* Reserved					0x14 */
#define PP2_MIB_BROADCAST_FRAMES_RECEIVED	0x18
#define PP2_MIB_MULTICAST_FRAMES_RECEIVED	0x1c
#define PP2_MIB_FRAMES_64_OCTETS			0x20
#define PP2_MIB_FRAMES_65_TO_127_OCTETS		0x24
#define PP2_MIB_FRAMES_128_TO_255_OCTETS		0x28
#define PP2_MIB_FRAMES_256_TO_511_OCTETS		0x2c
#define PP2_MIB_FRAMES_512_TO_1023_OCTETS	0x30
#define PP2_MIB_FRAMES_1024_TO_MAX_OCTETS	0x34
#define PP2_MIB_GOOD_OCTETS_SENT_LOW		0x38
#define PP2_MIB_GOOD_OCTETS_SENT_HIGH		0x3c
#define PP2_MIB_UNICAST_FRAMES_SENT		0x40
/* Reserved					0x44 */
#define PP2_MIB_MULTICAST_FRAMES_SENT		0x48
#define PP2_MIB_BROADCAST_FRAMES_SENT		0x4c
/* Reserved					0x50 */
#define PP2_MIB_FC_SENT				0x54
#define PP2_MIB_FC_RECEIVED			0x58
#define PP2_MIB_RX_FIFO_OVERRUN			0x5c
#define PP2_MIB_UNDERSIZE_RECEIVED		0x60
#define PP2_MIB_FRAGMENTS_RECEIVED		0x64
#define PP2_MIB_OVERSIZE_RECEIVED		0x68
#define PP2_MIB_JABBER_RECEIVED			0x6c
#define PP2_MIB_MAC_RECEIVE_ERROR		0x70
#define PP2_MIB_BAD_CRC_EVENT			0x74
#define PP2_MIB_COLLISION			0x78
#define PP2_MIB_LATE_COLLISION			0x7c

/*************/
/*   PTP  REGS    */
/*************/

/* Ptp General Control */
#define PP2_PTP_GENERAL_CTRL_REG					(0x0808)
#define PP2_PTP_GENERAL_CTRL_PTP_UNIT_ENABLE_OFFS		0
#define PP2_PTP_GENERAL_CTRL_PTP_UNIT_ENABLE_MASK    \
		(0x00000001 << PP2_PTP_GENERAL_CTRL_PTP_UNIT_ENABLE_OFFS)

#define PP2_PTP_GENERAL_CTRL_PTP_RESET_OFFS		1
#define PP2_PTP_GENERAL_CTRL_PTP_RESET_MASK    \
		(0x00000001 << PP2_PTP_GENERAL_CTRL_PTP_RESET_OFFS)

#define PP2_PTP_GENERAL_CTRL_INTERFACE_WIDTH_SELECT_OFFS		2
#define PP2_PTP_GENERAL_CTRL_INTERFACE_WIDTH_SELECT_MASK    \
		(0x00000003 << PP2_PTP_GENERAL_CTRL_INTERFACE_WIDTH_SELECT_OFFS)

#define PP2_PTP_GENERAL_CTRL_CLEAR_COUNTERS_OFFS		4
#define PP2_PTP_GENERAL_CTRL_CLEAR_COUNTERS_MASK    \
		(0x00000001 << PP2_PTP_GENERAL_CTRL_CLEAR_COUNTERS_OFFS)

#define PP2_PTP_GENERAL_CTRL_TAI_SELECT_OFFS		5
#define PP2_PTP_GENERAL_CTRL_TAI_SELECT_MASK    \
		(0x00000001 << PP2_PTP_GENERAL_CTRL_TAI_SELECT_OFFS)

#define PP2_PTP_GENERAL_CTRL_TS_QUEUE_OVER_WRITE_ENABLE_OFFS		6
#define PP2_PTP_GENERAL_CTRL_TS_QUEUE_OVER_WRITE_ENABLE_MASK    \
	(0x00000001 << PP2_PTP_GENERAL_CTRL_TS_QUEUE_OVER_WRITE_ENABLE_OFFS)

#define PP2_PTP_GENERAL_CTRL_TAI_ACK_DELAY_OFFS		7
#define PP2_PTP_GENERAL_CTRL_TAI_ACK_DELAY_MASK    \
		(0x0000001f << PP2_PTP_GENERAL_CTRL_TAI_ACK_DELAY_OFFS)

/* Ptp Tx Timestamp Queue0 Reg0 */
#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_REG				(0x080c)
#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_PTP_TX_TIMESTAMP_QUEUE0_VALID_OFFS 0
#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_PTP_TX_TIMESTAMP_QUEUE0_VALID_MASK    \
	(0x00000001 << \
	PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_PTP_TX_TIMESTAMP_QUEUE0_VALID_OFFS)

#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_QUEUE_ID_OFFS		1
#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_QUEUE_ID_MASK    \
		(0x000003ff << PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_QUEUE_ID_OFFS)

#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_TAI_SELECT_OFFS		11
#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_TAI_SELECT_MASK    \
		(0x00000001 << PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_TAI_SELECT_OFFS)

#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_TOD_UPDATE_FLAG_OFFS		12
#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_TOD_UPDATE_FLAG_MASK    \
	(0x00000001 << PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_TOD_UPDATE_FLAG_OFFS)

#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_TIMESTAMP_BITS_0_2_OFFS		13
#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_TIMESTAMP_BITS_0_2_MASK    \
	(0x00000007 << PP2_PTP_TX_TIMESTAMP_QUEUE0_REG0_TIMESTAMP_BITS_0_2_OFFS)

/* Ptp Tx Timestamp Queue0 Reg1 */
#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG1_REG				(0x0810)
#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG1_TIMESTAMP_BITS_3_18_OFFS	0
#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG1_TIMESTAMP_BITS_3_18_MASK    \
	(0x0000ffff << \
	PP2_PTP_TX_TIMESTAMP_QUEUE0_REG1_TIMESTAMP_BITS_3_18_OFFS)

/* Ptp Tx Timestamp Queue0 Reg2 */
#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG2_REG				(0x0814)
#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG2_TIMESTAMP_BITS_19_31_OFFS	0
#define PP2_PTP_TX_TIMESTAMP_QUEUE0_REG2_TIMESTAMP_BITS_19_31_MASK    \
	(0x00001fff << \
	PP2_PTP_TX_TIMESTAMP_QUEUE0_REG2_TIMESTAMP_BITS_19_31_OFFS)

/* Ptp Tx Timestamp Queue1 Reg0 */
#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_REG				(0x0818)
#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_PTP_TX_TIMESTAMP_QUEUE1_VALID_OFFS 0
#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_PTP_TX_TIMESTAMP_QUEUE1_VALID_MASK    \
	(0x00000001 << \
	PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_PTP_TX_TIMESTAMP_QUEUE1_VALID_OFFS)

#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_QUEUE_ID_OFFS		1
#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_QUEUE_ID_MASK    \
		(0x000003ff << PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_QUEUE_ID_OFFS)

#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_TAI_SELECT_OFFS		11
#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_TAI_SELECT_MASK    \
		(0x00000001 << PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_TAI_SELECT_OFFS)

#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_TOD_UPDATE_FLAG_OFFS		12
#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_TOD_UPDATE_FLAG_MASK    \
	(0x00000001 << PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_TOD_UPDATE_FLAG_OFFS)

#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_TIMESTAMP_BITS_0_2_OFFS		13
#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_TIMESTAMP_BITS_0_2_MASK    \
	(0x00000007 << PP2_PTP_TX_TIMESTAMP_QUEUE1_REG0_TIMESTAMP_BITS_0_2_OFFS)

/* Ptp Tx Timestamp Queue1 Reg1 */
#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG1_REG				(0x081c)
#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG1_TIMESTAMP_BITS_3_18_OFFS	0
#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG1_TIMESTAMP_BITS_3_18_MASK    \
	(0x0000ffff << PP2_PTP_TX_TIMESTAMP_QUEUE1_REG1_TIMESTAMP_BITS_3_18_OFFS)

/* Ptp Tx Timestamp Queue1 Reg2 */
#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG2_REG				(0x0820)
#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG2_TIMESTAMP_BITS_19_31_OFFS	0
#define PP2_PTP_TX_TIMESTAMP_QUEUE1_REG2_TIMESTAMP_BITS_19_31_MASK    \
	(0x00001fff << \
	PP2_PTP_TX_TIMESTAMP_QUEUE1_REG2_TIMESTAMP_BITS_19_31_OFFS)

/* Total Ptp Packets Counter */
#define PP2_PTP_TOTAL_PTP_PCKTS_CNTR_REG				(0x0824)
#define PP2_PTP_TOTAL_PTP_PCKTS_CNTR_TOTAL_PTP_PACKETS_COUNTER_OFFS	0
#define PP2_PTP_TOTAL_PTP_PCKTS_CNTR_TOTAL_PTP_PACKETS_COUNTER_MASK    \
	(0x000000ff << \
	PP2_PTP_TOTAL_PTP_PCKTS_CNTR_TOTAL_PTP_PACKETS_COUNTER_OFFS)

/* Ptpv1 Packet Counter */
#define PP2_PTP_PTPV1_PCKT_CNTR_REG				(0x0828)
#define PP2_PTP_PTPV1_PCKT_CNTR_PTPV1_PACKET_COUNTER_OFFS		0
#define PP2_PTP_PTPV1_PCKT_CNTR_PTPV1_PACKET_COUNTER_MASK    \
	(0x000000ff << PP2_PTP_PTPV1_PCKT_CNTR_PTPV1_PACKET_COUNTER_OFFS)

/* Ptpv2 Packet Counter */
#define PP2_PTP_PTPV2_PCKT_CNTR_REG				(0x082c)
#define PP2_PTP_PTPV2_PCKT_CNTR_PTPV2_PACKET_COUNTER_OFFS		0
#define PP2_PTP_PTPV2_PCKT_CNTR_PTPV2_PACKET_COUNTER_MASK    \
	(0x000000ff << PP2_PTP_PTPV2_PCKT_CNTR_PTPV2_PACKET_COUNTER_OFFS)

/* Y1731 Packet Counter */
#define PP2_PTP_Y1731_PCKT_CNTR_REG				(0x0830)
#define PP2_PTP_Y1731_PCKT_CNTR_Y1731_PACKET_COUNTER_OFFS		0
#define PP2_PTP_Y1731_PCKT_CNTR_Y1731_PACKET_COUNTER_MASK    \
	(0x000000ff << PP2_PTP_Y1731_PCKT_CNTR_Y1731_PACKET_COUNTER_OFFS)

/* Ntpts Packet Counter */
#define PP2_PTP_NTPTS_PCKT_CNTR_REG				(0x0834)
#define PP2_PTP_NTPTS_PCKT_CNTR_NTPTS_PACKET_COUNTER_OFFS		0
#define PP2_PTP_NTPTS_PCKT_CNTR_NTPTS_PACKET_COUNTER_MASK    \
	(0x000000ff << PP2_PTP_NTPTS_PCKT_CNTR_NTPTS_PACKET_COUNTER_OFFS)

/* Ntpreceive Packet Counter */
#define PP2_PTP_NTPRECEIVE_PCKT_CNTR_REG				(0x0838)
#define PP2_PTP_NTPRECEIVE_PCKT_CNTR_NTPRX_PACKET_COUNTER_OFFS		0
#define PP2_PTP_NTPRECEIVE_PCKT_CNTR_NTPRX_PACKET_COUNTER_MASK    \
	(0x000000ff << PP2_PTP_NTPRECEIVE_PCKT_CNTR_NTPRX_PACKET_COUNTER_OFFS)

/* Ntptransmit Packet Counter */
#define PP2_PTP_NTPTRANSMIT_PCKT_CNTR_REG			(0x083c)
#define PP2_PTP_NTPTRANSMIT_PCKT_CNTR_NTPTX_PACKET_COUNTER_OFFS		0
#define PP2_PTP_NTPTRANSMIT_PCKT_CNTR_NTPTX_PACKET_COUNTER_MASK    \
	(0x000000ff << PP2_PTP_NTPTRANSMIT_PCKT_CNTR_NTPTX_PACKET_COUNTER_OFFS)

/* Wamp Packet Counter */
#define PP2_PTP_WAMP_PCKT_CNTR_REG				(0x0840)
#define PP2_PTP_WAMP_PCKT_CNTR_WAMP_PACKET_COUNTER_OFFS		0
#define PP2_PTP_WAMP_PCKT_CNTR_WAMP_PACKET_COUNTER_MASK    \
		(0x000000ff << PP2_PTP_WAMP_PCKT_CNTR_WAMP_PACKET_COUNTER_OFFS)

/* None Action Packet Counter */
#define PP2_PTP_NONE_ACTION_PCKT_CNTR_REG			(0x0844)
#define PP2_PTP_NONE_ACTION_PCKT_CNTR_NONE_ACTION_PACKET_COUNTER_OFFS	0
#define PP2_PTP_NONE_ACTION_PCKT_CNTR_NONE_ACTION_PACKET_COUNTER_MASK    \
	(0x000000ff << \
	PP2_PTP_NONE_ACTION_PCKT_CNTR_NONE_ACTION_PACKET_COUNTER_OFFS)

/* Forward Action Packet Counter */
#define PP2_PTP_FORWARD_ACTION_PCKT_CNTR_REG			(0x0848)
#define PP2_PTP_FORWARD_ACTION_PCKT_CNTR_FORWARD_ACTION_PACKET_COUNTER_OFFS 0
#define PP2_PTP_FORWARD_ACTION_PCKT_CNTR_FORWARD_ACTION_PACKET_COUNTER_MASK    \
	(0x000000ff << \
	PP2_PTP_FORWARD_ACTION_PCKT_CNTR_FORWARD_ACTION_PACKET_COUNTER_OFFS)

/* Drop Action Packet Counter */
#define PP2_PTP_DROP_ACTION_PCKT_CNTR_REG			(0x084c)
#define PP2_PTP_DROP_ACTION_PCKT_CNTR_DROP_ACTION_PACKET_COUNTER_OFFS	0
#define PP2_PTP_DROP_ACTION_PCKT_CNTR_DROP_ACTION_PACKET_COUNTER_MASK    \
	(0x000000ff << \
	PP2_PTP_DROP_ACTION_PCKT_CNTR_DROP_ACTION_PACKET_COUNTER_OFFS)

/* Capture Action Packet Counter */
#define PP2_PTP_CAPTURE_ACTION_PCKT_CNTR_REG			(0x0850)
#define PP2_PTP_CAPTURE_ACTION_PCKT_CNTR_CAPTURE_ACTION_PACKET_COUNTER_OFFS 0
#define PP2_PTP_CAPTURE_ACTION_PCKT_CNTR_CAPTURE_ACTION_PACKET_COUNTER_MASK    \
	(0x000000ff << \
	PP2_PTP_CAPTURE_ACTION_PCKT_CNTR_CAPTURE_ACTION_PACKET_COUNTER_OFFS)

/* Addtime Action Packet Counter */
#define PP2_PTP_ADDTIME_ACTION_PCKT_CNTR_REG			(0x0854)
#define PP2_PTP_ADDTIME_ACTION_PCKT_CNTR_ADDTIME_ACTION_PACKET_COUNTER_OFFS 0
#define PP2_PTP_ADDTIME_ACTION_PCKT_CNTR_ADDTIME_ACTION_PACKET_COUNTER_MASK    \
	(0x000000ff << \
	PP2_PTP_ADDTIME_ACTION_PCKT_CNTR_ADDTIME_ACTION_PACKET_COUNTER_OFFS)

/* Addcorrectedtime Action Packet Counter */
#define PP2_PTP_ADDCORRECTEDTIME_ACTION_PCKT_CNTR_REG		(0x0858)
#define PP2_PTP_ADDCORRECTEDTIME_ACTION_PACKET_COUNTER_OFFS	0
#define PP2_PTP_ADDCORRECTEDTIME_ACTION_PACKET_COUNTER_MASK    \
	(0x000000ff << PP2_PTP_ADDCORRECTEDTIME_ACTION_PACKET_COUNTER_OFFS)

/* Captureaddtime Action Packet Counter */
#define PP2_PTP_CAPTUREADDTIME_ACTION_PCKT_CNTR_REG		(0x085c)
#define PP2_PTP_CAPTUREADDTIME_ACTION_PACKET_COUNTER_OFFS	0
#define PP2_PTP_CAPTUREADDTIME_ACTION_PACKET_COUNTER_MASK    \
	(0x000000ff << PP2_PTP_CAPTUREADDTIME_ACTION_PACKET_COUNTER_OFFS)

/* Captureaddcorrectedtime Action Packet Counter */
#define PP2_PTP_CAPTUREADDCORRECTEDTIME_ACTION_PCKT_CNTR_REG	(0x0860)
#define PP2_PTP_CAPTUREADDCORRECTEDTIME_ACTION_PACKET_COUNTER_OFFS	0
#define PP2_PTP_CAPTUREADDCORRECTEDTIME_ACTION_PACKET_COUNTER_MASK    \
	(0x000000ff << \
	PP2_PTP_CAPTUREADDCORRECTEDTIME_ACTION_PACKET_COUNTER_OFFS)

/* Addingresstime Action Packet Counter */
#define PP2_PTP_ADDINGRESSTIME_ACTION_PCKT_CNTR_REG		(0x0864)
#define PP2_PTP_ADDINGRESSTIME_ACTION_PACKET_COUNTER_OFFS	0
#define PP2_PTP_ADDINGRESSTIME_ACTION_PACKET_COUNTER_MASK    \
	(0x000000ff << PP2_PTP_ADDINGRESSTIME_ACTION_PACKET_COUNTER_OFFS)

/* Captureaddingresstime Action Packet Counter */
#define PP2_PTP_CAPTUREADDINGRESSTIME_ACTION_PCKT_CNTR_REG	(0x0868)
#define PP2_PTP_CAPTUREADDINGRESSTIME_ACTION_PACKET_COUNTER_OFFS	0
#define PP2_PTP_CAPTUREADDINGRESSTIME_ACTION_PACKET_COUNTER_MASK    \
	(0x000000ff << PP2_PTP_CAPTUREADDINGRESSTIME_ACTION_PACKET_COUNTER_OFFS)

/* Captureingresstime Action Packet Counter */
#define PP2_PTP_CAPTUREINGRESSTIME_ACTION_PCKT_CNTR_REG		(0x086c)
#define PP2_PTP_CAPTUREINGRESSTIME_ACTION_PACKET_COUNTER_OFFS	0
#define PP2_PTP_CAPTUREINGRESSTIME_ACTION_PACKET_COUNTER_MASK    \
	(0x000000ff << PP2_PTP_CAPTUREINGRESSTIME_ACTION_PACKET_COUNTER_OFFS)

/* Ntp Ptp Offset High */
#define PP2_PTP_NTP_PTP_OFFSET_HIGH_REG				(0x0870)
#define PP2_PTP_NTP_PTP_OFFSET_HIGH_PTP_NTP_OFFSET_HIGH_OFFS	0
#define PP2_PTP_NTP_PTP_OFFSET_HIGH_PTP_NTP_OFFSET_HIGH_MASK    \
	(0x0000ffff << PP2_PTP_NTP_PTP_OFFSET_HIGH_PTP_NTP_OFFSET_HIGH_OFFS)

/* Ntp Ptp Offset Low */
#define PP2_PTP_NTP_PTP_OFFSET_LOW_REG				(0x0874)
#define PP2_PTP_NTP_PTP_OFFSET_LOW_PTP_NTP_OFFSET_LOW_OFFS	0
#define PP2_PTP_NTP_PTP_OFFSET_LOW_PTP_NTP_OFFSET_LOW_MASK    \
	(0x0000ffff << PP2_PTP_NTP_PTP_OFFSET_LOW_PTP_NTP_OFFSET_LOW_OFFS)

/******************************************************************************/
/* System Soft Reset 1 */
#define PP2_GOP_SOFT_RESET_1_REG		0x108

#define NETC_GOP_SOFT_RESET_OFFSET		6
#define NETC_GOP_SOFT_RESET_MASK	(0x1 << NETC_GOP_SOFT_RESET_OFFSET)

/* Ports Control 0 */
#define PP2_NETCOMP_PORTS_CONTROL_0	(0x110)

#define NETC_CLK_DIV_PHASE_OFFSET		31
#define NETC_CLK_DIV_PHASE_MASK		(0x1 << NETC_CLK_DIV_PHASE_OFFSET)

#define NETC_GIG_RX_DATA_SAMPLE_OFFSET		29
#define NETC_GIG_RX_DATA_SAMPLE_MASK	(0x1 << NETC_GIG_RX_DATA_SAMPLE_OFFSET)

#define NETC_BUS_WIDTH_SELECT_OFFSET		1
#define NETC_BUS_WIDTH_SELECT_MASK	(0x1 << NETC_BUS_WIDTH_SELECT_OFFSET)

#define NETC_GOP_ENABLE_OFFSET			0
#define NETC_GOP_ENABLE_MASK		(0x1 << NETC_GOP_ENABLE_OFFSET)

/* Ports Control 1 */
#define PP2_NETCOMP_PORTS_CONTROL_1	(0x114)

#define NETC_PORT_GIG_RF_RESET_OFFSET(port)	(28 + port)
#define NETC_PORT_GIG_RF_RESET_MASK(port)	\
	(0x1 << NETC_PORT_GIG_RF_RESET_OFFSET(port))

#define NETC_PORTS_ACTIVE_OFFSET(port)		(0 + port)
#define NETC_PORTS_ACTIVE_MASK(port)	(0x1 << NETC_PORTS_ACTIVE_OFFSET(port))

/* Ports Status */
#define PP2_NETCOMP_PORTS_STATUS		(0x11C)
#define NETC_PORTS_STATUS_OFFSET(port)		(0 + port)
#define NETC_PORTS_STATUS_MASK(port)	(0x1 << NETC_PORTS_STATUS_OFFSET(port))

/* Networking Complex Control 0 */
#define PP2_NETCOMP_CONTROL_0		(0x120)

#define NETC_GBE_PORT1_MII_MODE_OFFSET		2
#define NETC_GBE_PORT1_MII_MODE_MASK	\
	(0x1 << NETC_GBE_PORT1_MII_MODE_OFFSET)

#define NETC_GBE_PORT1_SGMII_MODE_OFFSET	1
#define NETC_GBE_PORT1_SGMII_MODE_MASK	\
	(0x1 << NETC_GBE_PORT1_SGMII_MODE_OFFSET)

#define NETC_GBE_PORT0_SGMII_MODE_OFFSET	0
#define NETC_GBE_PORT0_SGMII_MODE_MASK	\
	(0x1 << NETC_GBE_PORT0_SGMII_MODE_OFFSET)

/* ComPhy Selector */
#define COMMON_PHYS_SELECT_REG		(0x40)

#define COMMON_PHYS_SELECT_LANE_OFFSET(lane)	(4 * lane)
#define COMMON_PHYS_SELECT_LANE_MASK(lane)    \
	(0xF << COMMON_PHYS_SELECT_LANE_OFFSET(lane))
#define COMMON_PHYS_SELECT_LANE_UNCONNECTED	(0x0)

#define COMMON_PHYS_SELECT_LANE_0_ETH2		(0x1)
#define COMMON_PHYS_SELECT_LANE_1_ETH3    \
	(0x1 << COMMON_PHYS_SELECT_LANE_OFFSET(1))
#define COMMON_PHYS_SELECT_LANE_2_ETH0    \
	(0x1 << COMMON_PHYS_SELECT_LANE_OFFSET(2))
#define COMMON_PHYS_SELECT_LANE_3_ETH1    \
	(0x1 << COMMON_PHYS_SELECT_LANE_OFFSET(3))
#define COMMON_PHYS_SELECT_LANE_3_ETH2    \
	(0x2 << COMMON_PHYS_SELECT_LANE_OFFSET(3))
#define COMMON_PHYS_SELECT_LANE_4_ETH2    \
	(0x1 << COMMON_PHYS_SELECT_LANE_OFFSET(4))
#define COMMON_PHYS_SELECT_LANE_4_ETH0    \
	(0x2 << COMMON_PHYS_SELECT_LANE_OFFSET(4))
#define COMMON_PHYS_SELECT_LANE_5_ETH3    \
	(0x1 << COMMON_PHYS_SELECT_LANE_OFFSET(5))
#define COMMON_PHYS_SELECT_LANE_5_ETH1    \
	(0x2 << COMMON_PHYS_SELECT_LANE_OFFSET(5))

/* SD1 Control1 */
#define SD1_CONTROL_1_REG		(0x148)

#define SD1_CONTROL_XAUI_EN_OFFSET		28
#define SD1_CONTROL_XAUI_EN_MASK	(0x1 << SD1_CONTROL_XAUI_EN_OFFSET)

#define SD1_CONTROL_RXAUI0_L23_EN_OFFSET	27
#define SD1_CONTROL_RXAUI0_L23_EN_MASK	(0x1 << \
					SD1_CONTROL_RXAUI0_L23_EN_OFFSET)

#define SD1_CONTROL_RXAUI1_L45_EN_OFFSET	26
#define SD1_CONTROL_RXAUI1_L45_EN_MASK	(0x1 << \
					SD1_CONTROL_RXAUI1_L45_EN_OFFSET)

/******************************************************************************/

#define PCS40G_COMMON_CONTROL					(0x014)

#define FORWARD_ERROR_CORRECTION_OFFSET			10
#define FORWARD_ERROR_CORRECTION_MASK	(0x1 << FORWARD_ERROR_CORRECTION_OFFSET)

#define PCS_CLOCK_RESET							(0x14C)

#define CLK_DIV_PHASE_SET_OFFSET					11
#define CLK_DIV_PHASE_SET_MASK	(0x1 << CLK_DIV_PHASE_SET_OFFSET)

#define CLK_DIVISION_RATIO_OFFSET				4
#define CLK_DIVISION_RATIO_MASK	(0x7 << CLK_DIVISION_RATIO_OFFSET)

#define MAC_CLK_RESET_OFFSET					2
#define MAC_CLK_RESET_MASK		(0x1 << MAC_CLK_RESET_OFFSET)

#define RX_SD_CLK_RESET_OFFSET					1
#define RX_SD_CLK_RESET_MASK	(0x1 << RX_SD_CLK_RESET_OFFSET)

#define TX_SD_CLK_RESET_OFFSET					0
#define TX_SD_CLK_RESET_MASK	(0x1 << TX_SD_CLK_RESET_OFFSET)

#endif /*_PP2_GOP_DEF_H_*/
